AD7091RBRMZ Datasheet, PDF (18/20 Pages) Analog Devices – 1 MSPS, Ultralow Power, 12-Bit ADC in 10-Lead LFCSP and MSOP

AD7091R
Data Sheet
SOFTWARE RESET
The AD7091R requires the user to initiate a software reset when
power is first applied. It should be noted that failure to apply
the correct software reset command may result in a device
malfunction.
To issue a software reset,
1. Start a conversion.
2. Read back the conversion result by pulling CS low after the
conversion is complete.
3. Between the second and eighth SCLK cycles, pull CS high
to short cycle the read operation.
4. At the end of the next conversion, the software reset is
executed.
If using the on-chip internal reference, the user should wait until
the reference capacitor is fully charged to meet the specified
performance.
The timing diagram for this operation is shown in Figure 31.
INTERFACING WITH 8-/16-BIT SPI
It is also possible to interface the AD7091R with a conventional
8-/16-bit SPI bus.
Performing conversions and reading results can be achieved by
configuring the host SPI interface to 16 bits, which results in
providing an additional four SCLK cycles to complete a conversion
compared with the standard interface methods (see the With
BUSY Indicator and Without BUSY Indicator sections). After
the 13^th SCLK falling edge with the BUSY indicator feature
enabled or the 12^th SCLK falling edge with the BUSY indicator
feature disabled, SDO returns to a high impedance state. The
additional four bits should be treated as don’t cares by the host.
All other timings are as outlined in Figure 27 and Figure 28,
with tQUIET starting after the 16^th SCLK cycle.
A software reset can be performed by configuring the SPI bus to
eight bits and performing the operation outlined in the Software
Reset section.
CONVST
CS
EOC
t₇
t₈
t₁₂
SDO
t₁₀
CONVERSION DATA
NOTES
1. DON’T CARE.
2. EOC IS THE END OF A CONVERSION.
Figure 29. Serial Interface Read Timing—Normal Mode
CONVST
CS
EOC
POWER-DOWN MODE
t₈
t₁₃
t₁₂
SDO
t₁₀
CONVERSION DATA
NOTES
1. DON’T CARE.
2. EOC IS THE END OF A CONVERSION.
Figure 30. Entering/Exiting Power-Down Mode
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