AD5763 Datasheet, PDF (18/31 Pages) Analog Devices – Complete Dual, 16-Bit, High Accuracy, Serial Input, ±5V DACs

AD5763
THEORY OF OPERATION
The AD5763 is a Dual, 16-bit, serial input, bipolar voltage output
DAC and operates from supply voltages of ±4.75 V to ±5.25 V and
has a buffered output voltage of up to ±4.311 V. Data is written to
the AD5763 in a 24-bit word format, via a 3-wire serial interface.
The device also offers an SDO pin, which is available for daisy-
chaining or readback.
The AD5763 incorporates a power-on reset circuit, which
ensures that the DAC registers power up loaded with 0x0000.
The AD5763 features a digital I/O port that can be programmed
via the serial interface, on-chip reference buffers and per
channel digital gain, and offset registers.
DAC ARCHITECTURE
The DAC architecture of the AD5763 consists of a 16-bit
current mode segmented R-2R DAC. The simplified circuit
diagram for the DAC section is shown in Figure 31.
The four MSBs of the 16-bit data word are decoded to drive 15
switches, E1 to E15. Each of these switches connects one of the
15 matched resistors to either AGNDX or IOUT. The remaining
12 bits of the data-word drive switches S0 to S11 of the 12-bit
R-2R ladder network.
V_REF
R
R
R
2R 2R
2R
2R 2R
2R 2R
E15 E14
E1 _{S11 S10}
S0
R/8
IOUT
AGNDX
4 MSBs DECODED INTO
15 EQUAL SEGMENTS
12-BIT, R-2R LADDER
Figure 31. DAC Ladder Structure
VOUTX
REFERENCE BUFFERS
The AD5763 operates with an external reference. The reference
inputs (REFA and REFB) have an input range up to 2.1 V. This
input voltage is then used to provide a buffered positive and
negative reference for the DAC cores. The positive reference is
given by
+VREF = 2VREF
The negative reference to the DAC cores is given by
−VREF = −2VREF
These positive and negative reference voltages (along with the
gain register values) define the output ranges of the DACs.
Preliminary Technical Data
SERIAL INTERFACE
The AD5763 is controlled over a versatile 3-wire serial interface
that operates at clock rates of up to 30 MHz and is compatible
with SPI®, QSPI™, MICROWIRE™, and DSP standards.
Input Shift Register
The input shift register is 24 bits wide. Data is loaded into the
device MSB first as a 24-bit word under the control of a serial
clock input, SCLK. The input register consists of a read/write
bit, three register select bits, three DAC address bits and 16 data
bits as shown in Table 8. The timing diagram for this operation
is shown in Figure 2.
Upon power-up, the DAC registers are loaded with zero code
(0x0000) and the outputs are clamped to 0 V via a low impedance
path. The outputs can be updated with the zero code value at this
time by asserting either LDAC or CLR. The corresponding output
voltage depends on the state of the BIN/2sCOMP pin. If the
BIN/2sCOMP pin is tied to DGND, then the data coding is twos
complement and the outputs update to 0 V. If the BIN/2sCOMP
pin is tied to DVCC, then the data coding is offset binary and the
outputs update to negative full-scale. To have the outputs power-up
with zero code loaded to the outputs, the CLR pin should be held
low during power-up.
Standalone Operation
The serial interface works with both a continuous and noncon-
tinuous serial clock. A continuous SCLK source can only be
used if SYNC is held low for the correct number of clock cycles.
In gated clock mode, a burst clock containing the exact number
of clock cycles must be used and SYNC must be taken high after
the final clock to latch the data. The first falling edge of SYNC
starts the write cycle. Exactly 24 falling clock edges must be
applied to SCLK before SYNC is brought back high again. If
SYNC is brought high before the 24^th falling SCLK edge, then
the data written is invalid. If more than 24 falling SCLK edges
are applied before SYNC is brought high, then the input data is
also invalid. The input register addressed is updated on the
rising edge of SYNC. In order for another serial transfer to take
place, SYNC must be brought low again. After the end of the
serial data transfer, data is automatically transferred from the
input shift register to the addressed register.
When the data has been transferred into the chosen register of
the addressed DAC, all DAC registers and outputs can be
updated by taking LDAC low.
Rev. PrA | Page 18 of 31