AD5316_15 Datasheet, PDF (18/24 Pages) Analog Devices – 2.5 V to 5.5 V, 400 A, 2-Wire Interface, Quad Voltage Output, 8-/10-/12-Bit DACs

AD5306/AD5316/AD5326
WRITE OPERATION
When writing to the AD5306/AD5316/AD5326 DACs, the user
must begin with an address byte (R/W = 0), after which the DAC
acknowledges that it is prepared to receive data by pulling SDA
low. This address byte is followed by the pointer byte, which is
also acknowledged by the DAC. Two bytes of data are then
written to the DAC, as shown in Figure 33. A stop condition
follows.
READ OPERATION
When reading data back from the AD5306/AD5316/AD5326
DACs, the user begins with an address byte (R/W = 0), after
which the DAC acknowledges that it is prepared to receive data
by pulling SDA low. This address byte is usually followed by the
pointer byte, which is also acknowledged by the DAC. Following
this, there is a repeated start condition by the master, and the
address is resent with R/W = 1. This is acknowledged by the
DAC, indicating that it is prepared to transmit data. Two bytes
of data are then read from the DAC, as shown in Figure 34. A
stop condition follows.
SCL
SDA
0
0
0
1
1
A1
A0
R/W
X
X
START
CONDITION
BY
MASTER
ADDRESS BYTE
ACK MSB
BY
AD533x
POINTER BYTE
LSB
ACK
BY
AD53x6
SCL
SDA
MSB
MOST SIGNIFICANT DATA BYTE
LSB
ACK
BY
AD53x6
MSB
LEAST SIGNIFICANT DATA BYTE
Figure 33. Write Sequence
LSB
ACK
BY
AD53x6
STOP
CONDITION
BY
MASTER
SCL
SDA
0
0
0
11
A1
A0
R/W
X
X
START
CONDITION
BY
MASTER
ADDRESS BYTE
ACK MSB
BY
AD53x6
POINTER BYTE
LSB
ACK
BY
AD53x6
SCL
SDA
0
REPEATED
START
CONDITION
BY
MASTER
0
0
11
ADDRESS BYTE
A1
A0 R/W
MSB
ACK
BY
AD53x6
DATA BYTE
LSB
ACK
BY
MASTER
SCL
SDA
MSB
LEAST SIGNIFICANT DATA BYTE
LSB
NO
ACK
BY
MASTER
STOP
CONDITION
BY
MASTER
Figure 34. Readback Sequence
Rev. F | Page 18 of 24