ADV7183B_15 Datasheet, PDF (17/100 Pages) Analog Devices – Multiformat SDTV Video Decoder

GLOBAL PIN CONTROL
Three-State Output Drivers
TOD, Address 0x03[6]
This bit allows the user to three-state the output drivers of the
ADV7183B.
Upon setting the TOD bit, the P15 to P0, HS, VS, FIELD, and
SFL pins are three-stated.
The timing pins (HS/VS/FIELD) can be forced active via the
TIM_OE bit. For more information on three-state control, refer
to the 149HThree-State LLC Driver and the Timing 150H Signals Output
Enable sections.
Individual drive strength controls are provided via the
DR_STR_XX bits.
The ADV7183B supports three-stating via a dedicated pin.
When set high, the OE pin three-states the output drivers for
the P15 to P0, HS, VS, FIELD, and SFL pins. The output drivers
are three-stated if the TOD bit or the OE pin is set high.
When TOD is 0 (default), the output drivers are enabled.
When TOD is 1, the output drivers are three-stated.
Three-State LLC Driver
TRI_LLC, Address 0x1D[7]
This bit allows the output drivers for the LLC1 and LLC2 pins
of the ADV7183B to be three-stated. For more information on
three-state control, refer to the 15HThree-State Output Drivers and
the Timing 152H Signals Output Enable sections.
Individual drive strength controls are provided via the
DR_STR_XX bits.
When TRI_LLC is 0 (default), the LLC pin drivers work
according to the DR_STR_C[1:0] setting (pin enabled).
When TRI_LLC is 1, the LLC pin drivers are three-stated.
ADV7183B
Timing Signals Output Enable
TIM_OE, Address 0x04[3]
The TIM_OE bit should be regarded as an addition to the TOD
bit. Setting it high forces the output drivers for HS, VS, and
FIELD pins into the active (driving) state even if the TOD bit is
set. If set to low, the HS, VS, and FIELD pins are three-stated,
dependent on the TOD bit. This functionality is useful if the
decoder is used as a timing generator only. This can happen
when only the timing signals are to be extracted from an
incoming signal, or if the part is in free-run mode where a
separate chip can output, for an example, a company logo.
For more information on three-state control, refer to the Three- 153H
State Output Drivers and the 154HThree-State LLC Driver sections.
Individual drive strength controls are provided via the
DR_STR_XX bits.
When TIM_OE is 0 (default), the HS, VS, and FIELD pins are
three-stated according to the TOD bit.
When TIM_OE is 1, HS, VS, and FIELD are forced active all
the time.
Drive Strength Selection (Data)
DR_STR[1:0] Address 0xF4[5:4]
For EMC and crosstalk reasons, it can be desirable to strengthen
or weaken the drive strength of the output drivers. The
DR_STR[1:0] bits affect the P[15:0] output drivers.
For more information on three-state control, refer to the Drive 15H
Strength Selection (Clock) and the Drive 156H Strength Selection
(Sync) sections.
Table 11. DR_STR Function
DR_STR[1:0]
Description
00
Low drive strength (1×)
01 (default)
Medium low drive strength (2×)
10
Medium high drive strength (3×)
11
High drive strength (4×)
Rev. B | Page 17 of 100