ADUM4154 Datasheet, PDF (17/22 Pages) Analog Devices – 5 kV, 7-Channel, SPIsolator Multiple Slave, Digital Isolator for SPI

Data Sheet
APPLICATIONS INFORMATION
INTRODUCTION
The ADuM4154 was created to optimize isolation of the SPI for
speed and to provide additional low speed channels for control
and status monitoring functions. The isolator is based on
differential signaling iCoupler technology for enhanced speed
and noise immunity.
High Speed Channels
The ADuM4154 has four high speed channels. The first three
channels, CLK, MI/SO, and MO/SI (the slash indicates the
connection of the particular input and output channel across
the isolator), are optimized for either low propagation delay in
the B grade, or high noise immunity in the A grade. The
difference between the grades is the addition of a glitch filter to
these three channels in the A grade version, which increases the
propagation delay. The B grade version, with a maximum
propagation delay of 14 ns, supports a maximum clock rate of
17 MHz in standard 4-wire SPI. However, because the glitch
filter is not present in the B grade version, ensure that spurious
glitches of less than 10 ns are not present.
Glitches of less than 10 ns in the B grade devices can cause the
second edge of the glitch to be missed. This pulse condition is
then seen as a spurious data transition on the output that is
corrected by a refresh or the next valid data edge. It is recommended
to use the A grade devices in noisy environments.
The relationship between the SPI signal paths and the pin
mnemonics of the ADuM4154 and data directions is detailed in
Table 20.
Table 20. Pin Mnemonics Correspondence to SPI Signal Path
Names
SPI Signal
Master
Data
Slave
Path
Side 1
Direction
Side 2
CLK
MCLK
→
SCLK
MO/SI
MO
→
SI
MI/SO
MI
←
SO
SS
MSS
→
SSx
The datapaths are SPI mode agnostic. The CLK and MO/SI SPI
datapaths are optimized for propagation delay and channel to
channel matching. The MI/SO SPI datapath is optimized for
propagation delay. The device does not synchronize to the clock
channel; therefore, there are no constraints on the clock polarity
or the timing with respect to the data line. To allow
compatibility with nonstandard SPI interfaces, the MI pin is
always active, and does not tristate when the slave select is not
asserted. This precludes tying several MI lines together without
adding a trisate buffer or multiplexor.
ADuM4154
SS (slave select bar) is typically an active low signal. SS can have
many different functions in SPI and SPI like busses. Many of
these functions are edge triggered; therefore, the SS path contains a
glitch filter in both the A grade and the B grade. The glitch filter
prevents short pulses from propagating to the output or causing
other errors in operation. The MSS signal requires a 10 ns setup
time in the B grade devices prior to the first active clock edge to
allow the added propagation time of the glitch filter.
Slave Select Multiplexer
The ADuM4154 can control up to four independent slave
devices. Figure 10 shows how this can be done using general-
purpose isolators. An isolation channel is required for each
slave select; therefore, seven high speed channels are required to
transfer bidirectional data to four slaves.
MASTER
ISOLATOR
CLK
MOSI
MISO
SS0
CLK SLAVE 0
MOSI
MISO
SS0
SS1
CLK SLAVE 1
SS2
MOSI
SS3
MISO
SS1
CLK SLAVE 2
MOSI
MISO
SS2
CLK SLAVE 3
MOSI
MISO
SS3
Figure 10. Multiple Slave Control with Standard Isolators
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