ADUC7021_15 Datasheet, PDF (17/104 Pages) Analog Devices – Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU

Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
Table 7. SPI Master Mode Timing (Phase Mode = 0)
Parameter
Description
tSL
SCLK low pulse width¹
tSH
SCLK high pulse width¹
tDAV
Data output valid after SCLK edge
tDOSU
Data output setup before SCLK edge
tDSU
Data input setup time before SCLK edge²
tDHD
Data input hold time after SCLK edge²
tDF
Data output fall time
tDR
Data output rise time
tSR
SCLK rise time
tSF
SCLK fall time
Min
1 × tUCLK
2 × tUCLK
Typ
(SPIDIV + 1) × tHCLK
(SPIDIV + 1) × tHCLK
5
5
5
5
1 _{tHCLK depends on the clock divider or CD bits in the POWCONMMR. tHCLK = tUCLK/2}CD_{; see Figure 67.}
2 _{tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider; see Figure 67.}
Max
25
75
12.5
12.5
12.5
12.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK
(POLARITY = 0)
SCLK
(POLARITY = 1)
MOSI
t_SH
t_SL
t_DOSU
t_DAV
t_DF
MSB
t_DR
BITS 6 TO 1
t_SR
t_SF
LSB
MISO
MSB IN
BITS 6 TO 1
LSB IN
t_DSU
t_DHD
Figure 16. SPI Master Mode Timing (Phase Mode = 0)
Rev. F | Page 17 of 104