AD9528 Datasheet, PDF (17/68 Pages) Analog Devices – Maximum output frequency

AD9528
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Data Sheet
VDD 1
REFA 2
REFA 3
REF_SEL 4
REFB 5
REFB 6
LF1 7
VCXO_VT 8
NIC 9
VDD 10
VCXO_IN 11
VCXO_IN 12
NIC 13
LF2_CAP 14
LDO_VCO 15
VDD 16
NIC 17
NIC 18
AD9528
TOP VIEW
(Not to Scale)
54 VDD4
53 OUT4
52 OUT4
51 VDD5
50 OUT5
49 OUT5
48 VDD6
47 OUT6
46 OUT6
45 VDD7
44 OUT7
43 OUT7
42 VDD8
41 OUT8
40 OUT8
39 VDD9
38 OUT9
37 OUT9
NOTES
1. NIC = NO INTERNAL CONNECTION. THIS PIN CAN BE LEFT FLOATING.
2. THE EXPOSED PAD IS THE GROUND CONNECTION ON THE CHIP.
IT MUST BE SOLDERED TO THE ANALOG GROUND OF THE PCB TO ENSURE
PROPER FUNCTIONALITY AND HEAT DISSIPATION, NOISE, AND MECHANICAL
STRENGTH BENEFITS.
Figure 2. Pin Configuration
Table 21. Pin Function Descriptions
Pin
No. Mnemonic
Type¹ Description
1 VDD
P
3.3 V Supply for the PLL1 Input Section.
2 REFA
I
Reference Clock Input A. Along with REFA, this pin is the differential input for the PLL reference.
Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.
3 REFA
I
Complementary Reference Clock Input A. Along with REFA, this pin is the differential input for the
PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.
4 REF_SEL
I
Reference Input Select. The reference input selection function defaults to software control via
internal Register 0x010A, Bits[2:0]. When the REF_SEL pin is active, a logic low selects REFA and logic
high selects REFB.
5 REFB
I
Reference Clock Input B. Along with REFB, this pin is the differential input for the PLL reference.
Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.
6 REFB
I
Complementary Reference Clock Input B. Along with REFB, this pin is the differential input for the PLL
reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.
7 LF1
O
PLL1 External Loop Filter.
8 VCXO_VT
O
VCXO Control Voltage. Connect this pin to the voltage control pin of the external VCXO.
9 NIC
NIC
No Internal Connection. The pin can be left floating.
10 VDD
P
3.3 V Supply for the PLL2 Section.
11 VCXO_IN
I
PLL1 Oscillator Input. Along with VCXO_IN, this pin is the differential input for the PLL reference.
Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.
12 VCXO_IN
I
Complementary PLL1 Oscillator Input. Along with VCXO_IN, this pin is the differential input for the
PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.
13 NIC
NIC
No Internal Connection. The pin can be left floating.
14 LF2_CAP
O
PLL2 External Loop Filter Capacitor Connection. Connect capacitor between this pin and the
LDO_VCO pin.
Rev. C | Page 16 of 67