AD7981_17 Datasheet, PDF (17/26 Pages) Analog Devices – High Temperature, 16-Bit, 600 kSPS PulSAR ADC

Data Sheet
VOLTAGE REFERENCE INPUT
The AD7981 voltage reference input, REF, has a dynamic input
impedance and must therefore be driven by a low impedance
source with efficient decoupling between the REF and GND
pins, as explained in the Printed Circuit Board (PCB) Layout
section.
When REF is driven by a very low impedance source, a ceramic
chip capacitor is appropriate for optimum performance. The
high temperature qualified low temperature drift ADR225 2.5 V
reference and the low power AD8634 reference buffer are
recommended for the AD7981.
The REF pin must be decoupled with a ceramic chip capacitor of
at least 10 μF (X5R, 1206 size) for optimum performance.
There is no need for an additional lower value ceramic decoupling
capacitor (for example, 100 nF) between the REF and GND pins.
POWER SUPPLY
The AD7981 uses two power supply pins: a core supply, VDD, and
a digital input/output interface supply, VIO. VIO allows direct
interfacing with any logic between 1.8 V and 5 V. To reduce the
number of supplies needed, tie VIO and VDD together. The
AD7981 is independent of power supply sequencing between
VIO and VDD. Additionally, it is insensitive to power supply
variations over a wide frequency range, as shown in Figure 40.
80
75
70
65
60
55
1
10
100
1000
FREQUENCY (kHz)
Figure 40. PSRR vs. Frequency
The AD7981 powers down automatically at the end of each
conversion phase and, therefore, the power scales linearly with
the sampling rate, which makes the device ideal for low sampling
rate (even of a few Hz) and low battery-powered applications.
1
VDD = 2.5V
V_REF = 5V
VIO = 3V
0.1
0.01
AD7981
I_VDD
I_REF
I_VIO
0.001
10000
100000
THROUGHPUT RATE (SPS)
600000
Figure 41. Operating Currents vs. Throughput Rate
DIGITAL INTERFACE
Although the AD7981 has a reduced number of pins, it offers
flexibility in its serial interface modes.
The AD7981, when in CS mode, is compatible with SPI, QSPI™,
MICROWIRE™, and digital hosts. The AD7981 interface can
use either a 3-wire or 4-wire interface. A 3-wire interface using
the CNV, SCK, and SDO signals minimizes wiring connections
and is useful, for instance, in isolated applications. A 4-wire
interface using the SDI, CNV, SCK, and SDO signals allows
CNV, which initiates the conversions, to be independent of the
readback timing (SDI). The 4-wire interface is useful in low jitter
sampling or simultaneous sampling applications.
The AD7981, when in chain mode, provides a daisy-chain feature
using the SDI input for cascading multiple ADCs on a single
data line, similar to a shift register.
The mode in which the device operates depends on the SDI
level when the CNV rising edge occurs. CS mode is selected if
SDI is high, and chain mode is selected if SDI is low. The SDI
hold time is such that, when SDI and CNV are connected
together, chain mode is selected.
In either mode, the AD7981 offers the flexibility to optionally
force a start bit in front of the data bits. This start bit can be used as
a busy signal indicator to interrupt the digital host and to trigger
the data reading. Otherwise, without a busy indicator, the user
must time out the maximum conversion time prior to readback.
The busy indicator feature is enabled in the following modes:
 In CS mode if CNV or SDI is low when the ADC conversion
ends (see Figure 45 and Figure 49, respectively).
 In chain mode if SCK is high during the CNV rising edge
(see Figure 53).
Rev. B | Page 17 of 26