AD768 Datasheet, PDF (17/20 Pages) Analog Devices – 16-Bit, 30 MSPS D/A Converter

R5
499
+V_{CC C5}
U2
0.1µF
2
7
6
A
3 ^AD811 _C6
4 0.1µF
A
A
–V_EE
R7
100
R_∞8
AD768
A
1
2
B
1
2
JP5
50
R10
499
50
T1
3
1
4:1
45
6
R2
R3
24.9
24.9
A
JP1
JP2
A
JP3
JP4
R9
100
+V_{CC C7}
U3
0.1µF
2
7
6A
AD811
3
C8
4 _0.1µF
A
–V_EE
A
C9
47µF, 25V
C10
0.1µF
R_∞6
C11
47µF, 25V
A
C12
0.1µF
–V_EE
+V_CC
A
R12
10k
1
SW2
TP1
J1 31 ^R13
J1 29 ^R14
J1 27 ^R15
J1 25 ^R16
J1 23 ^R17
J1 21 ^R18
J1 19 ^R19
J1 17 ^R20
2
0
0
0
0
0
0
0
0
A
C1
1µF
R1
499
C2
C18
1µF 0.1µF
U1
AD768
1
28
IOUTA
LADCOM
2
27
NR
IOUTB
3
26
REFOUT
4
(–5V) V_{EE 25}
NC
5
(+5V) V_{DD 24}
REFCOM (MSB) DB15
6
23
IREFIN
DB14
7
22
DB0 (LSB)
DB13
8
21
DB1
DB12
9
20
DB2
DB11
10
19
DB3
DB10
11
18
DB4
DB9
12
17
DB5
DB8
13
16
DB6
CLOCK
14
15
DB7
DCOM
C3
C17
1µF 0.1µF
A
C4
1µF
C19
0.1µF
–5A
C13
C14
47µF, 25V
0.1µF
A
C15
47µF, 25V
R21
R23
R24
R25
R26
R27
R28
R29
C16
0.1µF
0
1
0
3
0
5
0
7
0
9
0
11
0
13
0 ₁₅
+5D
J1
J1
J1
J1
J1
J1
J1
J1
J1 33
CLOCK
1
2
1
SW1
2
R11
50
J1 2
J1 4
J1 6
J1 8
J1 10
J1 12
J1 14
J1 16
J1 18
J1 20
J1 22
J1 24
J1 26
J1 28
J1 30
J1 32
J1 34
J1 36
J1 38
J1 40
Figure 35. AD768 Evaluation Board Schematic
DGND
AGND CONNECTED TO DGND
ON GND PLANE UNDER U1
IN BETWEEN PINS 5 AND 25
AGND
A
REV. B
–17–