AD73311ARSZ Datasheet, PDF (17/36 Pages) Analog Devices – Low Cost, Low Power CMOS General Purpose Analog Front End

CONTROL REGISTER A
Table XI. Control Register A Description
7
6
RESET DC2
5
DC1
4
3
DC0 DLB
2
ALB
1
0
MM
DATA/
PGM
AD73311
CONTROL REGISTER B
Bit Name
Description
0 DATA/PGM Operating Mode (0 = Program; 1 = Data Mode)
1 MM
Mixed Mode (0 = Off; 1 = Enabled)
2 ALB
Analog Loop-Back Mode (0 = Off; 1 = Enabled)
3 DLB
Digital Loop-Back Mode (0 = Off; 1 = Enabled)
4 DC0
Device Count (Bit 0)
5 DC1
Device Count (Bit 1)
6 DC2
Device Count (Bit 2)
7 RESET
Software Reset (0 = Off; 1 = Initiates Reset)
Table XII. Control Register B Description
7
6
5
4
3
2
1
0
CEE MCD2 MCD1 MCD0 SCD1 SCD0
1
1
Bit Name
0 Reserved
1 Reserved
2 SCD0
3 SCD1
4 MCD0
5 MCD1
6 MCD2
7 CEE
Description
Must Be Programmed to 1
Must Be Programmed to 1
Serial Clock Divider (Bit 0)
Serial Clock Divider (Bit 1)
Master Clock Divider (Bit 0)
Master Clock Divider (Bit 1)
Master Clock Divider (Bit 2)
Control Echo Enable (0 = Off; 1 = Enabled)
CONTROL REGISTER C
Table XIII. Control Register C Description
7
6
5
4
3
2
5VEN RU PUREF PUDAC PUADC 0
1
0
0
PU
Bit Name
0 PU
1 Reserved
2 Reserved
3 PUADC
4 PUDAC
5 PUREF
6 RU
7 5VEN
Description
Power-Up Device (0 = Power Down; 1 = Power On)
Must Be Programmed to 0
Must Be Programmed to 0
ADC Power (0 = Power Down; 1 = Power On)
DAC Power (0 = Power Down; 1 = Power On)
REF Power (0 = Power Down; 1 = Power On)
REFOUT Use (0 = Disable REFOUT; 1 = Enable
REFOUT)
Enable 5 V Operating Mode (0 = Disable 5 V Mode;
1 = Enable 5 V Mode)
REV. B
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