AD6652 Datasheet, PDF (17/76 Pages) Analog Devices – 12-Bit, 65 MSPS IF to Baseband Diversity Receiver

DDC TIMING DIAGRAMS
CLK
LIA, LIB
LIA, LIB
t_CLK
t_CLKL
t_CLKH
t_DLI
Figure 17. Level Indicator Output Switching Characteristics
CLK
PCLK
RESET
CLK
SYNCA
SYNCB
SYNCC
SYNCD
t_RESL
Figure 18. Reset Timing Requirements
t_SS
t_HS
Figure 19. SYNC Timing Inputs
t_DPOCLKL
Figure 20. PCLK to CLK Switching Characteristics Divide-by-1
CLK
PCLK
t_DPOCLKLL
t_POCLKH
t_POCLKL
Figure 21. PCLK to CLK Switching Characteristics Divide-by-2, -4, or -8
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AD6652