AD4020 Datasheet, PDF (17/37 Pages) Analog Devices – Precision SAR, Differential ADC

AD4020
When the acquisition phase is complete and the CNV input
goes high, a conversion phase initiates. When the conversion
phase begins, SW+ and SW− opens first. The two capacitor
arrays are then disconnected from the inputs and connected to
the GND input. The differential voltage between the IN+ and
IN− inputs captured at the end of the acquisition phase is
applied to the comparator inputs, causing the comparator to
become unbalanced. By switching each element of the capacitor
array between GND and VREF, the comparator input varies by
binary weighted voltage steps (VREF/2, VREF/4, …, VREF/1,048,576).
The control logic toggles these switches, starting with the MSB,
to bring the comparator back into a balanced condition. After
the completion of this process, the control logic generates the
ADC output code and a busy signal indicator.
Because the AD4020 has an on-board conversion clock, the
serial clock, SCK, is not required for the conversion process.
Data Sheet
TRANSFER FUNCTIONS
The ideal transfer characteristics for the AD4020 are shown in
Figure 30 and Table 9.
011...111
011...110
011...101
100...010
100...001
100...000
–FSR
–FSR + 1 LSB
–FSR + 0.5 LSB
+FSR – 1 LSB
+FSR – 1.5 LSB
ANALOG INPUT
Figure 30. ADC Ideal Transfer Function (FSR Is Full-Scale Range)
Table 9. Output Codes and Ideal Input Voltages
Description
Analog Input, VREF = 5 V
FSR − 1 LSB
+4.99999046 V
Midscale + 1 LSB +9.54 µV
Midscale
0V
Midscale − 1 LSB −9.54 µV
−FSR + 1 LSB
−4.99999046 V
−FSR
−5 V
VREF = 5 V with Span Compression Enabled
+3.99999237 V
+7.63 µV
0V
−7.63 µV
−3.99999237 V
−4 V
1 _{This output code is also the code for an overranged analog input (VIN+ − VIN− above VREF).}
2 _{This output code is also the code for an underranged analog input (VIN+ − VIN− below −VREF).}
Digital Output Code (Hex)
0x7FFFF¹
0x00001
0x00000
0xFFFFF
0x80001
0x80000²
Rev. A | Page 16 of 36