ADSP-2186M_15 Datasheet, PDF (16/40 Pages) Analog Devices – DSP Microcomputer

ADSP-2186M
These 32 words are used to set up the BDMA to load in the
remaining program code. The BCR bit is also set to 1, which
causes program execution to be held off until all 32 words are
loaded into on-chip program memory. Execution then begins at
address 0.
The ADSP-2100 Family development software (Revision 5.02
and later) fully supports the BDMA booting feature and can
generate byte-memory space-compatible boot code.
The IDLE instruction can also be used to allow the processor
to hold off execution while booting continues through the
BDMA interface. For BDMA accesses while in Host Mode, the
addresses to boot memory must be constructed externally to the
ADSP-2186M. The only memory address bit provided by the
processor is A0.
IDMA Port Booting
The ADSP-2186M can also boot programs through its Internal
DMA port. If Mode C = 1, Mode B = 0, and Mode A = 1, the
ADSP-2186M boots from the IDMA port. IDMA feature can
load as much on-chip memory as desired. Program execution is
held off until on-chip program memory location 0 is written to.
Bus Request and Bus Grant
The ADSP-2186M can relinquish control of the data and address
buses to an external device. When the external device requires
access to memory, it asserts the bus request (BR) signal. If the
ADSP-2186M is not performing an external memory access, it
responds to the active BR input in the following processor cycle by:
• Three-stating the data and address buses and the PMS, DMS,
BMS, CMS, IOMS, RD, WR output drivers,
• Asserting the bus grant (BG) signal, and
• Halting program execution.
If Go Mode is enabled, the ADSP-2186M will not halt program
execution until it encounters an instruction that requires an
external memory access.
If the ADSP-2186M is performing an external memory access
when the external device asserts the BR signal, it will not three-
state the memory interfaces nor assert the BG signal until the
processor cycle after the access completes. The instruction does
not need to be completed when the bus is granted. If a single
instruction requires two external memory accesses, the bus will
be granted between the two accesses.
When the BR signal is released, the processor releases the BG
signal, re-enables the output drivers, and continues program
execution from the point at which it stopped.
The bus request feature operates at all times, including when
the processor is booting and when RESET is active.
The BGH pin is asserted when the ADSP-2186M requires the
external bus for a memory or BDMA access, but is stopped.
The other device can release the bus by deasserting bus request.
Once the bus is released, the ADSP-2186M deasserts BG and
BGH and executes the external memory access.
Flag I/O Pins
The ADSP-2186M has eight general purpose programmable
input/output flag pins. They are controlled by two memory
mapped registers. The PFTYPE register determines the direc-
tion, 1 = output and 0 = input. The PFDATA register is used to
read and write the values on the pins. Data being read from a
pin configured as an input is synchronized to the ADSP-2186M’s
clock. Bits that are programmed as outputs will read the value
being output. The PF pins default to input during reset.
In addition to the programmable flags, the ADSP-2186M has five
fixed-mode flags, FI, FO, FL0, FL1, and FL2. FL0–FL2 are
dedicated output flags. FI and FO are available as an alternate
configuration of SPORT1.
Note: Pins PF0, PF1, PF2, and PF3 are also used for device
configuration during reset.
Instruction Set Description
The ADSP-2186M assembly language instruction set has an
algebraic syntax that was designed for ease of coding and read-
ability. The assembly language, which takes full advantage of the
processor’s unique architecture, offers the following benefits:
• The algebraic syntax eliminates the need to remember cryptic
assembler mnemonics. For example, a typical arithmetic add
instruction, such as AR = AX0 + AY0, resembles a simple
equation.
• Every instruction assembles into a single, 24-bit word that
can execute in a single instruction cycle.
• The syntax is a superset ADSP-2100 Family assembly lan-
guage and is completely source and object code compatible
with other family members. Programs may need to be relocated
to utilize on-chip memory and conform to the ADSP-2186M’s
interrupt vector and reset vector map.
• Sixteen condition codes are available. For conditional jump,
call, return, or arithmetic instructions, the condition can
be checked and the operation executed in the same instruc-
tion cycle.
• Multifunction instructions allow parallel execution of an
arithmetic instruction with up to two fetches or one write to
processor memory space during a single instruction cycle.
DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM
The ADSP-2186M has on-chip emulation support and an
ICE-Port, a special set of pins that interface to the EZ-ICE.
These features allow in-circuit emulation without replacing the
target system processor by using only a 14-pin connection from
the target system to the EZ-ICE. Target systems must have a
14-pin connector to accept the EZ-ICE’s in-circuit probe, a
14-pin plug.
Issuing the chip reset command during emulation causes the
DSP to perform a full chip reset, including a reset of its memory
mode. Therefore, it is vital that the mode pins are set correctly
PRIOR to issuing a chip reset command from the emulator user
interface. If a passive method of maintaining mode information is
being used (as discussed in Setting Memory Modes), it does not
matter that the mode information is latched by an emulator
reset. However, if the RESET pin is being used as a method of
setting the value of the mode pins, the effects of an emulator
reset must be taken into consideration.
One method of ensuring that the values located on the mode
pins are those desired is to construct a circuit like the one shown
in Figure 12. This circuit forces the value located on the Mode
A pin to logic high; regardless of whether it is latched via the
RESET or ERESET pin.
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