ADF4360-1_15 Datasheet, PDF (16/24 Pages) Analog Devices – Integrated Synthesizer and VCO

ADF4360-1
POWER-UP
Power-Up Sequence
The correct programming sequence for the ADF4360-1 after
power-up is:
1. R counter latch
2. Control latch
3. N counter latch
Initial Power-Up
Initial power-up refers to programming the part after the
application of voltage to the AV_DD, DV_DD, V_VCO, and CE pins. On
initial power-up, an interval is required between programming
the control latch and programming the N counter latch. This
interval is necessary to allow the transient behavior of the
ADF4360-1 during initial power-up to have settled.
Data Sheet
During initial power-up, a write to the control latch powers up
the part and the bias currents of the VCO begin to settle. If the-
se currents have not settled to within 10% of their steady-state
value, and if the N counter latch is then programmed, the VCO
may not oscillate at the desired frequency, which does not allow
the band select logic to choose the correct frequency band and
the ADF4360-1 may not achieve lock. If the recommended in-
terval is inserted, and the N counter latch is programmed, the
band select logic can choose the correct frequency band, and
the part locks to the correct frequency.
The duration of this interval is affected by the value of the
capacitor on the C_N pin (Pin 14). This capacitor is used to
reduce the close-in noise of the ADF4360-1 VCO. The recom-
mended value of this capacitor is 10 µF. Using this value
requires an interval of ≥ 5 ms between the latching in of the
control latch bits and latching in of the N counter latch bits.
If a shorter delay is required, this capacitor can be reduced. A
slight phase noise penalty is incurred by this change, which is
explained in the Table 10.
Table 10. C_N Capacitance vs. Interval and Phase Noise
C_N Value Recommended Interval between Control Latch and N Counter Latch
10 µF
≥ 5 ms
440 nF
≥ 600 µs
Open-Loop Phase Noise @ 10 kHz Offset
−85 dBc
−84 dBc
POWER-UP
CLOCK
DATA
LE
R COUNTER
LATCH DATA
CONTROL
LATCH DATA
N COUNTER
LATCH DATA
REQUIRED INTERVAL
CONTROL LATCH WRITE TO
N COUNTER LATCH WRITE
Figure 16. ADF4360-1 Power-Up Timing
Rev. C | Page 16 of 24