AD9361BBCZ-REEL Datasheet, PDF (16/36 Pages) Analog Devices – RF Agile Transceiver

AD9361
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
A RX2A_N RX2A_P
NC
VSSA
TX_MON2
VSSA
TX2A_N
TX2A_P
TX2B_N
TX2B_P
VDDA1P1_ TX_EXT_
TX_VCO
LO_IN
B
VSSA
VSSA
AUXDAC1 GPO_3
GPO_2
GPO_1
GPO_0
VDD_GPO
VDDA1P3_
TX_LO
VDDA1P3_
TX_VCO_
LDO
TX_VCO_
LDO_OUT
VSSA
C RX2C_P
VSSA
AUXDAC2
TEST/
ENABLE
CTRL_IN0 CTRL_IN1
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
D
RX2C_N ^{VDDA1P3_ VDDA1P3_} CTRL_OUT0 CTRL_IN3 CTRL_IN2 ^P0_D9/
RX_RF
RX_TX
TX_D4_P
P0_D7/
TX_D3_P
P0_D5/
TX_D2_P
P0_D3/
TX_D1_P
P0_D1/
TX_D0_P
VSSD
E
RX2B_P
VDDA1P3_
RX_LO
VDDA1P3_
TX_LO_ CTRL_OUT1 CTRL_OUT2 CTRL_OUT3
BUFFER
P0_D11/
TX_D5_P
P0_D8/
TX_D4_N
P0_D6/
TX_D3_N
P0_D4/
TX_D2_N
P0_D2/
TX_D1_N
P0_D0/
TX_D0_N
VDDA1P3_
F RX2B_N RX_VCO_
VSSA CTRL_OUT6 CTRL_OUT5 CTRL_OUT4 VSSD
LDO
P0_D10/
TX_D5_N
VSSD FB_CLK_P
VSSD
VDDD1P3_
DIG
G
RX_EXT_ RX_VCO_ VDDA1P1_
LO_IN
LDO_OUT RX_VCO ^{CTRL_OUT7 EN_AGC}
RX_
RX_
TX_
ENABLE _{FRAME_N FRAME_P FRAME_P} FB_CLK_N
DATA_
CLK_P
VSSD
H RX1B_P
J RX1B_N
VSSA
VSSA
TXNRX
VSSA
VDDA1P3_
RX_SYNTH
SPI_DI
SYNC_IN
SPI_CLK
VSSA
VSSD
P1_D10/
CLK_OUT _{RX_D5_N}
P1_D11/
TX_
RX_D5_P FRAME_N
VSSD
P1_D9/
RX_D4_P
P1_D7/
RX_D3_P
P1_D5/
RX_D2_P
DATA_
VDD_
CLK_N INTERFACE
P1_D3/
P1_D1/
RX_D1_P RX_D0_P
K RX1C_P
VSSA
VDDA1P3_ VDDA1P3_
TX_SYNTH
BB
RESETB
P1_D8/
P1_D6/
P1_D4/
P1_D2/
P1_D0/
SPI_ENB _{RX_D4_N RX_D3_N RX_D2_N RX_D1_N RX_D0_N}
VSSD
L RX1C_N
VSSA
VSSA
RBIAS
AUXADC SPI_DO
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
M RX1A_P RX1A_N
NC
VSSA
ANALOG I/O
DIGITAL I/O
NO CONNECT
DC POWER
GROUND
TX_MON1 VSSA
TX1A_P
TX1A_N
TX1B_P
Figure 2. Pin Configuration, Top View
TX1B_N
XTALP
XTALN
Table 13. Pin Function Descriptions
Pin No.
Type¹ Mnemonic
A1, A2
I
RX2A_N, RX2A_P
A3, M3
NC
A4, A6, B1, B2, I
B12, C2, C7 to
C12, F3, H2,
H3, H6, J2, K2,
L2, L3, L7 to
L12, M4, M6
A5
I
A7, A8
O
A9, A10
O
A11
I
A12
I
B3
O
B4 to B7
O
B8
I
B9
I
B10
I
B11
O
C1, D1
I
NC
VSSA
TX_MON2
TX2A_N, TX2A_P
TX2B_N, TX2B_P
VDDA1P1_TX_VCO
TX_EXT_LO_IN
AUXDAC1
GPO_3 to GPO_0
VDD_GPO
VDDA1P3_TX_LO
VDDA1P3_TX_VCO_LDO
TX_VCO_LDO_OUT
RX2C_P, RX2C_N
Description
Receive Channel 2 Differential Input A. Alternatively, each pin can be used as a
single-ended input or combined to make a differential pair. Tie unused pins to
ground.
No Connect. Do not connect to these pins.
Analog Ground. Tie these pins directly to the VSSD digital ground on the printed
circuit board (one ground plane).
Transmit Channel 2 Power Monitor Input. If this pin is unused, tie it to ground.
Transmit Channel 2 Differential Output A. Tie unused pins to 1.3 V.
Transmit Channel 2 Differential Output B. Tie unused pins to 1.3 V.
Transmit VCO Supply Input. Connect to B11.
External Transmit LO Input. If this pin is unused, tie it to ground.
Auxiliary DAC 1 Output.
3.3 V Capable General-Purpose Outputs.
2.5 V to 3.3 V Supply for the AUXDAC and General-Purpose Output Pins. When
the VDD_GPO supply is not used, this supply must be set to 1.3 V.
Transmit LO 1.3 V Supply Input.
Transmit VCO LDO 1.3 V Supply Input. Connect to B9.
Transmit VCO LDO Output. Connect to A11 and a 1 µF bypass capacitor in series
with a 1 Ω resistor to ground.
Receive Channel 2 Differential Input C. Each pin can be used as a single-ended
input or combined to make a differential pair. These inputs experience
degraded performance above 3 GHz. Tie unused pins to ground.
Rev. D | Page 16 of 36