AD7825_15 Datasheet, PDF (16/28 Pages) Analog Devices – 3 V/5 V, 2 MSPS, 8-Bit, 1-/4-/8-Channel Sampling ADCs

AD7822/AD7825/AD7829
Mode 2 Operation (Automatic Power-Down)
When the AD7822/AD7825/AD7829 are operated in Mode 2
(see Figure 25), they automatically power down at the end of
a conversion. The CONVST signal is brought low to initiate
a conversion and is left logic low until after the EOC goes high,
that is, approximately 100 ns after the end of the conversion.
The state of the CONVST signal is sampled at this point (that is,
530 ns maximum after CONVST falling edge), and the AD7822/
AD7825/AD7829 power down as long as CONVST is low.
TRACK
120ns
HOLD
t₂
CONVST
t₁
EOC
The ADC is powered up again on the rising edge of the
CONVST signal. Superior power performance can be achieved
in this mode of operation by powering up the AD7822/AD7825/
AD7829 only to carry out a conversion. The parallel interface of
the AD7822/AD7825/AD7829 remains fully operational while
the ADCs are powered down. A read may occur while the part
is powered down, and, therefore, it does not necessarily need to
be placed within the EOC pulse, as shown in Figure 25.
TRACK
HOLD
CS
RD
DB0 TO DB7
t₃
Figure 24. Mode 1 Operation
VALID
DATA
CONVST
EOC
CS
RD
DB0 TO DB7
t_POWER-UP
POWER
DOWN
HERE
t₁
VALID
DATA
Figure 25. Mode 2 Operation
Rev. C | Page 16 of 28