AD7654 Datasheet, PDF (16/24 Pages) Analog Devices – Dual 2-Channel Simultaneous Sampling SAR 500 kSPS 16-Bit ADC

AD7654
CS = RD = 0
t₁
CNVST
BUSY
t₃
EOC t₁₀
DATA BUS ^{PREVIOUS CHANNEL A}
OR B
t₁₆
t₄
t₁₇
PREVIOUS CHANNEL B
OR NEW A
NEW A
OR B
that it is read only during the first half of the conversion
phase. This avoids any potential feedthrough between voltage
transients on the digital interface and the most critical analog
conversion circuitry.
The BYTESWAP pin allows a glueless interface to an 8-bit bus.
As shown in Figure 13, the LSB byte is output on D[7:0] and
the MSB is output on D[15:8] when BYTESWAP is low. When
BYTESWAP is high, the LSB and MSB bytes are swapped, the
LSB is output on D[15:8], and the MSB is output on D[7:0].
By connecting BYTESWAP to an address line, the 16-bit data
can be read in two bytes on either D[15:8] or D[7:0].
Figure 10. Master Parallel Data Timing for Read-
ing (Continuous Read)
CS
RD
BUSY
DATA BUS
CURRENT
CONVERSION
t₁₈
t₁₉
Figure 11. Slave Parallel Data Timing for Reading
(Read after Convert)
CS = 0
CNVST, RD
EOC
t₁
t₁₂
t₁₀
t₁₁
t₁₃
BUSY
t₄
t₃
DATA BUS
PREVIOUS
CONVERSION
t₁₈
t₁₉
Figure 12. Slave Parallel Data Timing for Reading
(Read during Convert)
PARALLEL INTERFACE
The AD7654 is configured to use the parallel interface (Figure 10)
when the SER/PAR is held low. The data can be read either
after each conversion, which is during the next acquisition phase
or during the other channel’s conversion, or during the following
conversion as shown, respectively, in Figures 11 and 12. When the
data is read during the conversion, however, it is recommended
CS
RD
BYTE
HI-Z
PINS D[15:8]
HI-Z
PINS D[7:0]
HIGH BYTE
t₁₈
LOW BYTE
HI-Z
LOW BYTE
t₁₈
HIGH BYTE
t₁₉
HI-Z
Figure 13. 8-Bit Parallel Interface
CS
RD
A/B
HI-Z
DATA BUS
CHANNEL A
CHANNEL B
HI-Z
t₁₈
t₂₀
Figure 14. A/B Channel Reading
The detailed functionality of A/B is explained in Figure 15.
When high, the data from channel A is available on the data bus.
When low, the data bus now carries output from channel B.
Note that channel A can be read immediately after conversion is
done (EOC), while channel B is still in its converting phase.
SERIAL INTERFACE
The AD7654 is configured to use the serial interface when the
SER/PAR is held high. The AD7654 outputs 32 bits of data,
MSB first, on the SDOUT pin. The order of the channels being
output is controlled by A/B. When high, channel A is output
first; when low, channel B is output first. Unlike in parallel
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