AD660_08 Datasheet, PDF (16/20 Pages) Analog Devices – Monolithic 16-Bit Serial/Byte DACPORT

AD660
In applications such as waveform generation, accurate timing of
the output samples is important to avoid noise that is induced
by jitter on the LDAC signal. In this example, the ADSP-210x
is set up to use the internal timer to interrupt the processor at
the precise and desired sample rate. When the timer interrupt
occurs, the 16-bit data word of the processor is written to the
transmit register (TXn). This causes the DSP to automatically
generate the TFS signal and begin transmission of the data.
ADSP-210x 74HC04
SCLK
DT
CS _AD660
DB0/DB8/SIN
TFS
DQ
74HC74
SER
LDAC
Figure 19. AD660 to ADSP-210x Interface
AD660 TO Z80 INTERFACE
Figure 20 shows a Zilog Z80 8-bit microprocessor connected to
the AD660 using the byte mode interface. The double-buffered
capability of the AD660 allows the microprocessor to indepen-
dently write to the low and high byte registers, and update the
DAC output. Processor speeds up to 6 MHz on the Z80 require
no extra wait states to interface with the AD660 when using a
74ALS138 as the address decoder.
The address decoder analyzes the input-output address produced
by the processor to select the function to be performed by the
AD660, qualified by the coincidence of the input/output request
(IORQ) and write (WR) pins. The least significant address bit
(A0) determines if the low or high byte register of the AD660 is
active. More significant address bits select between input register
loading, DAC output update, and unipolar or bipolar clear.
A typical Z80 software routine begins by writing the low byte of
the desired 16-bit DAC data to Address 0, followed by the high
byte to Address 1. The DAC output is then updated by activating
LDAC with a write to Address 2 (or Address 3). A clear to unipolar
zero occurs on a write to Address 4, and a clear to bipolar zero
is performed by a write to Address 5. The actual data written to
Address 2 through Address 5 is irrelevant. The decoder can easily
be expanded to control as many AD660 devices as required.
D0 TO D7
Z80
IORQ
WR
A0 TO A15
ADDRESS
DECODE
E2
Y2
E1
Y1
Y0
A1 TO A15
A0
DB0 TO DB7 SER +V_LL
CLR
LDAC
CS
AD660
HBE LBE DGND
Figure 20. Connections for 8-Bit Bus Interface
NOISE
In high resolution systems, noise is often the limiting factor. A
16-bit DAC with a 10 V span has an LSB size of 153 μV (−96 dB).
Therefore, the noise floor must remain below this level in the
frequency range of interest. The noise spectral density of the
AD660 is shown in Figure 21 and Figure 22. Figure 21 shows
the DAC output noise voltage spectral density for a 20 V span
excluding the reference. This figure shows the 1/f corner frequency
at 100 Hz and the wideband noise to be below 120 nV/√Hz.
Figure 22 shows the reference noise voltage spectral density and
shows the reference wideband noise to be below 125 nV/√Hz.
1k
100
10
1
1
10
100
1k
10k 100k 1M
10M
FREQUENCY (Hz)
Figure 21. DAC Output Noise Voltage Spectral Density
1k
100
10
1
1
10
100
1k
10k 100k 1M
10M
FREQUENCY (Hz)
Figure 22. Reference Noise Voltage Spectral Density
Rev. B | Page 16 of 20