OP462_15 Datasheet, PDF (15/20 Pages) Analog Devices – 15 MHz Rail-to-Rail Operational Amplifiers

Data Sheet
V_S = 5V
A_V = 1
100
C_L = 300pF
90
R_L = 10kΩ
WITH SNUBBER:
R_X = 140Ω
C_X = 10nF
10
0%
50mV
1µs
Figure 39. A Photo of a Nice Square Wave at the Output
The network operates in parallel with the load capacitor, CL,
and provides compensation for the added phase lag. The actual
values of the network resistor and capacitor are empirically
determined to minimize overshoot and maximize unity-gain
bandwidth. Table 6 shows a few sample snubber networks for
large load capacitors.
Table 6. Snubber Networks for Large Capacitive Loads
CLOAD
RX
CX
< 300 pF
140 Ω
10 nF
500 pF
100 Ω
10 nF
1 nF
80 Ω
10 nF
10 nF
10 Ω
47 nF
Higher load capacitance will reduce the unity-gain bandwidth
of the device. Figure 40 shows unity-gain bandwidth vs.
capacitive load. The snubber network does not provide any
increase in bandwidth, but it substantially reduces ringing and
overshoot, as shown between Figure 38 and Figure 39.
10
9
8
7
6
5
4
3
2
1
0
10pF
100pF
1nF
C_LOAD
10nF
Figure 40. Unity-Gain Bandwidth vs. CLOAD
TOTAL HARMONIC DISTORTION AND CROSSTALK
The OPx62 device family offers low total harmonic distortion
making it an excellent choice for audio applications. Figure 41
shows a graph of THD plus noise figures at 0.001% for the
OP462.
OP162/OP262/OP462
Figure 42 shows the worst case crosstalk between two amplifiers
in the OP462. A 1 V rms signal is applied to one amplifier while
measuring the output of an adjacent amplifier. Both amplifiers
are configured for unity gain and supplied with ±2.5 V.
0.010
V_S = ±2.5V
A_V = 1
V_IN = 1.0V rms
R_L = 10kΩ
BANDWIDTH:
<10Hz TO 22kHz
0.001
0.0001
20
100
1k
FREQUENCY (Hz)
Figure 41. THD + N vs. Frequency
10k 20k
–40
–50
A_V = 1
V_IN = 1.0V rms
(0dBV)
–60
–70
R_L
V_S
=
=
10kΩ
±2.5^�V
–80
–90
–100
–110
–120
–130
–140
20
100
1k
FREQUENCY (Hz)
Figure 42. Crosstalk vs. Frequency
10k 20k
PCB LAYOUT CONSIDERATIONS
Because the OP162/OP262/OP462 can provide gains at high
frequency, careful attention to board layout and component
selection is recommended. As with any high speed application,
a good ground plane is essential to achieve the optimum
performance. This can significantly reduce the undesirable
effects of ground loops and I × R losses by providing a low
impedance reference point. Best results are obtained with a
multilayer board design with one layer assigned to ground
plane.
Use chip capacitors for supply bypassing, with one end of the
capacitor connected to the ground plane and the other end
connected within 1/8 inch of each power pin. An additional
large tantalum electrolytic capacitor (4.7 µF to 10 µF) should be
connected in parallel. This capacitor provides current for fast,
large-signal changes at the device’s output; therefore, it does not
need to be placed as close to the supply pins.
Rev. H | Page 15 of 20