ADV7321_15 Datasheet, PDF (15/88 Pages) Analog Devices – Multiformat 216 MHz Video Encoder with Six NSV 12-Bit DACs

ADV7320/ADV7321
P_HSYNC
P_VSYNC
a
P_BLANK
Y9–Y0
b
a = 32 CLKCYCLES FOR 525p
a = 24 CLKCYCLES FOR 625p
AS RECOMMENDED BY STANDARD
b(MIN) = 244 CLKCYCLES FOR 525p
b(MIN) = 264 CLKCYCLES FOR 625p
Figure 16. PS 4:2:2 10-Bit Interleaved Input Timing Diagram
Cb Y Cr Y
S_HSYNC
S_VSYNC
S_BLANK
PAL = 24 CLK CYCLES
NTSC = 32 CLK CYCLES
S9–S0/Y9–Y0*
*SELECTED BY ADDRESS 0x01, BIT 7: SEE TABLE 21.
PAL = 264 CLOCK CYCLES
NTSC = 244 CLOCK CYCLES
Figure 17. SD Timing Input for Timing Mode 1
t₃
SDA
t₅
t₃
t₆
t₁
SCLK
t₂
t₇
t₄
t₁ = SCLOCK HIGH PULSE WIDTH
t₂ = SCLOCK LOW PULSE WIDTH
t₃ = HOLD TIME (START CONDITION)
t₄ = SETUP TIME (START CONDITION)
t₅ = DATA SETUP TIME
t₆ = SDATA, SCLOCK RISE TIME
t₇ = SDATA, SCLOCK FALL TIME
t₈ = SETUP TIME (STOP CONDITION)
Figure 18. MPU Port Timing Diagram
Cb Y Cr Y
t₈
Rev. A | Page 15 of 88