ADUC836_15 Datasheet, PDF (15/80 Pages) Analog Devices – MicroConverter, Dual 16-Bit ADCs with Embedded 62 kB Flash MCU

Stack Pointer (SP and SPH)
The SP SFR is the stack pointer and is used to hold an internal
RAM address that is called the “top of the stack.” The SP Register
is incremented before data is stored, during PUSH and CALL
executions. While the Stack may reside anywhere in on-chip RAM,
the SP Register is initialized to 07H after a reset. This causes the
stack to begin at location 08H.
As mentioned earlier, the ADuC836 offers an extended 11-bit
stack pointer. The three extra bits that make up the 11-bit stack
pointer are the 3 LSBs of the SPH byte located at B7H.
Program Status Word (PSW)
The PSW SFR contains several bits reflecting the current status
of the CPU as detailed in Table I.
SFR Address
Power-On Default Value
Bit Addressable
D0H
00H
Yes
Table I. PSW SFR Bit Designations
Bit
Name
Description
7
CY
Carry Flag
6
AC
Auxiliary Carry Flag
5
F0
General-Purpose Flag
4
RS1
Register Bank Select Bits
3
RS0
RS1 RS0 Selected Bank
0
0
0
0
1
1
1
0
2
1
1
3
2
OV
Overflow Flag
1
F1
General-Purpose Flag
0
P
Parity Bit
Power Control SFR (PCON)
The PCON SFR contains bits for power saving options and
general-purpose status flags, as shown in Table II.
The TIC (Wake-Up/RTC timer) can be used to accurately wake
up the ADuC836 from power-down at regular intervals. To use
the TIC to wake up the ADuC836 from power-down, the OSC_PD
bit in the PLLCON SFR must be clear and the TIC must be
enabled.
SFR Address
87H
Power-On Default Value
00H
Bit Addressable
No
ADuC836
Table II. PCON SFR Bit Designations
Bit
Name
Description
7
SMOD
Double UART Baud Rate
6
SERIPD
SPI Power-Down Interrupt Enable
5
INT0PD
INT0 Power-Down Interrupt Enable
4
ALEOFF Disable ALE Output
3
GF1
General-Purpose Flag Bit
2
GF0
General-Purpose Flag Bit
1
PD
Power-Down Mode Enable
0
IDL
Idle Mode Enable
ADuC836 CONFIGURATION SFR (CFG836)
The CFG836 SFR contains the necessary bits to configure the
internal XRAM and the extended SP. By default it configures
the user into 8051 mode, i.e., extended SP is disabled, internal
XRAM is disabled.
SFR Address
Power-On Default Value
Bit Addressable
AFH
00H
No
Table III. CFG836 SFR Bit Designations
Bit Name Description
7 EXSP Extended SP Enable. If this bit is set, the
stack will roll over from SPH/SP = 00FFH to
0100H. If this bit is clear, the SPH SFR will
be disabled and the stack will roll over from
SP = FFH to SP = 00H.
6 –––
Reserved for Future Use
5 –––
Reserved for Future Use
4 –––
Reserved for Future Use
3 –––
Reserved for Future Use
2 –––
Reserved for Future Use
1 –––
Reserved for Future Use
0 XRAMEN XRAM Enable Bit. If this bit is set, the in-
ternal XRAM will be mapped into the lower
2 Kbytes of the external address space. If this
bit is clear, the internal XRAM will not be
accessible and the external data memory will
be mapped into the lower 2 Kbytes of external
data memory (see Figure 3).
REV. A
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