ADIS16250_15 Datasheet, PDF (15/20 Pages) Analog Devices – Programmable Low Power Gyroscope

ADIS16250/ADIS16255
OPERATIONAL CONTROL
Internal Sample Rate
The internal sample rate defines how often data output
variables are updated, independent of the rate at which they
are read out on the SPI port. The SMPL_PRD register controls
the ADIS16250/ADIS16255 internal sample rate and has two
parts: a selectable time base and a multiplier. The sample
period can be calculated using the following equation:
TS = TB × (NS + 1)
where:
TS is the sample period.
TB is the time base.
NS is the increment setting.
The default value is the maximum 256 samples per second,
and the contents of this register are nonvolatile.
After completing the sleep period, the ADIS16250/ADIS16255 return
to normal operation. If measurements are required before sleep
period completion, the ADIS16250/ADIS16255 can be awakened
by putting the CS line in a zero logic state. Otherwise, the CS line
must be kept high to maintain sleep mode.
Table 17. SLP_CNT Register Definition
Address Scale¹ Default Format
0x3B, 0x3A 0.5 sec 0x0000 Binary
1 _{Scale is the weight of each LSB.}
Access
R/W
Table 18. SLP_CNT Bit Descriptions
Bit
Description
15:8
Not used
7:0
Data bits
Analog Bandwidth
Table 15. SMPL_PRD Register Definition
Address
Default
Format
0x37, 0x36 0x0001
N/A
Access
R/W
The analog bandwidth of the ADIS16250/ADIS16255 is 50 Hz.
This bandwidth can be reduced by placing an external capacitor
across the RATE and FILT pins. In this case, the analog bandwidth
can be calculated using the following equation:
Table 16. SMPL_PRD Bit Descriptions
fOUT = 1/(2 × π × ROUT × (COUT + 0.068 μF))
Bit Description
15:8 Not used
7 Time base, 0 = 1.953 ms, 1 = 60.54 ms
6:0 Multiplier
The following is an example calculation of the sample period
for the ADIS16250/ADIS16255:
If SMPL_PRD = 0x0007, B7…B0 = 00000111
B7 = 0 → TB = 1.953 ms
B6…B0 = 000000111 → NS = 7
TS = TB × (NS + 1) = 1.953 ms × (7 + 1) = 15.624 ms
fS = 1∕TS = 64 SPS
The sample rate setting has a direct impact on the SPI data
rate capability. For sample rates of 64 SPS and above, the SPI
SCLK can run at a rate up to 2.5 MHz. For sample rates
below 64 SPS, the SPI SCLK can run at a rate up to 1 MHz.
where:
ROUT = 45.22 kΩ.
COUT is the external capacitance.
Digital Filtering
The ADIS16250/ADIS16255 GYRO_OUT signal path has a nominal
analog bandwidth of 50 Hz. The ADIS16250 provides a Bartlett
Window FIR filter for additional noise reduction on all of the output
data registers. The SENS/AVG register stores the number of taps in
this filter in seven power-of-two step sizes (that is, 2^M = 1, 2, 4, 16,
32, 64, and 128). Filter setup requires one simple step: write the
appropriate M factor to the assigned bits in the SENS/AVG register.
The bit assignments are listed in Table 20. The following equation
offers a frequency response relationship for this filter:
H_B
(f
)
=
H_A² ( f )
⇒
H_A(f
)
=
sin(π × N
N × sin(π
×
×
f
f
×
×
t_S)
t_S)
The sample rate setting also affects the power dissipation.
0
When the sample rate is set below 64 SPS, the power dissipation
–20
reduces by a factor of 60%. The two different modes of
operation offer a system-level trade-off between performance
–40
N = 16
N=4
N=2
(sample rate, serial transfer rate) and power dissipation.
–60
Power Management
In addition to offering two different performance modes for
power optimization, the ADIS16250/ADIS16255 offer a
–80
–100
N = 128
programmable shutdown period. Writing the appropriate
–120
sleep time to the SLP_CNT register shuts the device down
for the specified time. The following example provides an
–140
illustration of this relationship:
B7 … B0 = 00000110
–160
0.001
0.01
0.1
1
FREQUENCY (f/fs)
Sleep period = 3 sec
Rev. D | Page 15 of 20
Figure 23. Bartlett Window FIR Frequency Response