ADF4360-2_15 Datasheet, PDF (15/24 Pages) Analog Devices – Integrated Synthesizer and VCO

Data Sheet
ADF4360-2
Table 9. R Counter Latch
BAND
SELECT
CLOCK
ANTI-
BACKLASH
PULSE
WIDTH
14-BIT REFERENCE COUNTER
CONTROL
BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
RSV RSV BSC2 BSC1 TMB LDP ABP2 ABP1 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 C2 (0) C1 (1)
THESE BITS ARE NOT
USED BY THE DEVICE
AND ARE DON'T CARE
BITS.
TEST MODE
BIT SHOULD
BE SET TO 0
FOR NORMAL
OPERATION.
R14
R13
R12
0
0
0
..........
0
0
0
..........
0
0
0
..........
0
0
0
..........
.
.
.
..........
.
.
.
..........
.
.
.
..........
1
1
1
..........
1
1
1
..........
1
1
1
..........
1
1
1
..........
LDP
0
1
ABP2
0
0
1
1
ABP1
0
1
0
1
ANTIBACKLASH PULSE WIDTH
3.0ns
1.3ns
6.0ns
3.0ns
LOCK DETECT PRECISION
THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
R3
R2
R1
0
0
0
0
1
1
0
1
0
1
0
1
.
.
.
.
.
.
.
.
.
1
0
0
1
0
1
1
1
0
1
1
1
DIVIDE RATIO
1
2
3
4
.
.
.
16380
16381
16382
16383
BSC2
0
0
1
1
BSC1
0
1
0
1
BAND SELECT CLOCK DIVIDER
1
2
4
8
Rev. C | Page 15 of 24