ADE7903 Datasheet, PDF (15/28 Pages) Analog Devices – 3-Channel, Sigma-Delta ADC with SPI

Data Sheet
the noise is shaped by the integrator, which has a high-pass type
response for the quantization noise. The result is that most of the
noise is at higher frequencies where it can be removed by the
digital low-pass filter. This noise shaping is shown in Figure 24.
The bandwidth of interest is a function of the input clock
frequency, the ADC output frequency (selectable by Bits[5:4]
(ADC_FREQ) in the CONFIG register; see the ADC Output
Values section for details), and Bit 7 (BW) of the CONFIG
register. When CLKIN is 4.096 MHz and the ADC output
frequency is 8 kHz, if BW is cleared to 0 (the default value), the
ADC bandwidth is 3.3 kHz. If BW is set to 1, the ADC bandwidth
is 2 kHz. Table 6 shows the ADC output frequencies and the
ADC bandwidth as a function of the input clock (CLKIN)
frequency. Three cases are shown: one for CLKIN = 4.096 MHz,
the typical clock input frequency value; one for CLKIN =
4.21 MHz, the maximum clock input frequency; and one for
CLKIN = 3.6 MHz, the minimum clock input frequency.
Antialiasing Filter
Figure 23 also shows an analog low-pass filter (RC) on the input
to the ADC. This filter is placed outside the ADE7903, and its role
is to prevent aliasing. Aliasing is an artifact of all sampled systems,
as shown in Figure 25. Aliasing refers to the frequency components
in the input signal to the ADC that are higher than half the
sampling rate of the ADC and appear in the sampled signal at a
frequency below half the sampling rate. Frequency components
above half the sampling frequency (also known as the Nyquist
frequency, that is, 512 kHz) are imaged or folded back down
below 512 kHz. This folding happens with all ADCs, regardless of
the architecture. In Figure 25, only frequencies near the sampling
frequency of 1.024 MHz move into the bandwidth of interest for
metering, that is, 40 Hz to 3.3 kHz or 40 Hz to 2 kHz. To attenuate
the high frequency noise (near 1.024 MHz) and prevent the
distortion of the bandwidth of interest, a low-pass filter must be
introduced. It is recommended that one RC filter with a corner
frequency of 5 kHz be used for the attenuation to be sufficiently
high at the sampling frequency of 1.024 MHz. The 20 dB per
ADE7903
decade attenuation of this filter is usually sufficient to eliminate
the effects of aliasing.
ALIASING EFFECTS
SAMPLING
FREQUENCY
0
24
512
FREQUENCY (kHz)
IMAGE
FREQUENCIES
1024
Figure 25. Aliasing Effects
ADC Transfer Function
All ADCs in the ADE7903 produce 24-bit signed output codes.
With a full-scale input signal of 31.25 mV on the current channel
and 0.5 V on the voltage channels, and with an internal reference
of 1.2 V, the ADC output code is nominally 5,320,000 and usually
varies for each ADE7903 around this value. The code from the
ADC can vary between 0x800000 (−8,388,608) and 0x7FFFFF
(+8,388,607), which is equivalent to an input signal level of
±49.27 mV on the current channel and ±0.788 V on the voltage
channels. However, for specified performance, do not exceed
the nominal range of ±31.25 mV for the current channel and
±500 mV for the voltage channels; ADC performance is
guaranteed only for input signals within these limits.
ADC Output Values
The ADC output values are stored in three 24-bit signed
registers, IWV, V1WV, and V2WV, at a rate defined by Bits[5:4]
(ADC_FREQ) in the CONFIG register. The output frequency is
8 kHz (CLKIN/512), 4 kHz (CLKIN/1024), 2 kHz (CLKIN/2048),
or 1 kHz (CLKIN/4096) based on ADC_FREQ being equal to
00, 01, 10, or 11, respectively, when CLKIN is 4.096 MHz.
The microcontroller reads the ADC output registers one at a time
or in burst mode. See the SPI Read Operation section and the SPI
Read Operation in Burst Mode section for more information.
Table 6. ADC Output Frequency and ADC Bandwidth as a Function of CLKIN Frequency
CLKIN
(MHz)
ADC_FREQ Bits in
CONFIG Register
ADC Output
Frequency (Hz)
ADC Bandwidth When BW Bit in
CONFIG Register Cleared to 0 (Hz)
4.096
00
8000
3300
01
4000
1650
10
2000
825
11
1000
412
4.21
00
8222
3391
01
4111
1695
10
2055
847
11
1027
423
3.6
00
7031
2900
01
3515
1450
10
1757
725
11
878
362
ADC Bandwidth When BW Bit in
CONFIG Register Set to 1 (Hz)
2000
1000
500
250
2055
1027
513
256
1757
878
439
219
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