AD9772 Datasheet, PDF (15/30 Pages) Analog Devices – 14-Bit, 150 MSPS TxDAC™ with 2x Interpolation Filter

AD9772
To disable the PLL Clock Multiplier, connect PLLVDD to
PLLCOM as shown in Figure 29. LPF may remain open since
this portion of the PLL circuitry is now disabled. The differen-
tial clock input should be driven with a reference clock twice the
data input rate in baseband applications and four time the data
input rate in direct IF applications in which the “1/4 wave”
mixing option is employed (i.e., MOD1 and MOD0 active
HIGH). The clock distribution circuitry remains enabled pro-
viding a 1× internal clock at PLLLOCK. Since the digital input
data is latched into the AD9772 with respect to the rising edge
of the 1× clock appearing at PLLLOCK, adequate setup and
hold time for the input data as shown in Figure 1b should be
allowed. Since PLLLOCK contains a weak driver output, its
output delay (t_OD) is sensitive to output capacitance loading.
Thus PLLLOCK should be buffered for fanouts greater than
one and/or load capacitance greater than 10 pF. If a data timing
issue exists between the AD9772 and its external driver device,
the 1× clock appearing at PLLLOCK can be inverted via an
external gate to ensure proper setup and hold time.
CLKVDD PLLLOCK
CLK+ CLK–
+–
AD9772
OUT1؋
CLOCK
DISTRIBUTION
PHASE
DETECTOR
EXT/INT
CLOCK CONTROL
CHARGE
PUMP
LPF
PLL
VDD
PRESCALER
VCO
PLL
COM
CLKCOM
Figure 29. Clock Multiplier with PLL CLOCK Multiplier
Disabled
CLOCK DOUBLER APPLICATION
A low phase noise 2× clock can be derived from a 1× clock by
using the clock doubler circuit shown in Figure 30. This circuit
is based on a low cost mixer (i.e., Mini-Circuits ADE-1) whose
IF and LO ports are driven with the same single-ended 1× sine
wave source via R-C quadrature phase shifting networks. Note it
is necessary to drive the IF and LO port with quadrature sine
waves to optimize the 2× clock signal level appearing at the RF
port. The value of R should be selected to match the source
resistance of the sine wave source (i.e., 50 Ω) while the value of
C should be selected such that the R-C cut-off frequency (i.e.,
f_{–3 dB}) occurs at approximately the 1× clock frequency. The
AD9772 differential CLK input is driven single-ended by the
mixer’s RF port while a low impedance common-mode voltage
of CLKVDD/2 for both devices is established by a 1 kΩ resistor
divider and 0.1 µF capacitor. The AD9772 experiences negli-
gible degradation in its noise floor due to additive clock jitter
with this clock doubler circuit as long as it is driven by a low
noise sine wave source.
SINE
WAVE
CLOCK
R
50⍀
C
33pF
R
50⍀
C
33pF
6
1
5
2
MINI-CIRCUITS
ADE-1
CLKVDD
3
CLK+
1k⍀ AD9772
4
CLK–
1k⍀
0.1␮F
Figure 30. Low Cost Clock Doubler Circuit Achieves Low
Phase Noise Performance
DAC OPERATION
The 14-bit DAC along with the 1.2 V reference and reference
control amplifier is shown in Figure 31. The DAC consists of a
large PMOS current source array capable of providing up to
20 mA of full-scale current, I_OUTFS. The array is divided into
thirty-one equal currents that make up the five most significant
bits (MSBs). The next four bits, or middle bits, consist of 15
equal current sources whose values are 1/16th of an MSB
current source. The remaining LSBs are binary weighted frac-
tions of the middle-bits’ current sources. All of these current
sources are switched to one or the other of two output nodes
(i.e., IOUTA or IOUTB) via PMOS differential current switches.
Implementing the middle and lower bits with current sources,
instead of an R-2R ladder, enhances its dynamic performance
for multitone or low amplitude signals and helps maintain the
DAC’s high output impedance.
The full-scale output current is regulated by the reference con-
trol amplifier and can be set from 2 mA to 20 mA via an exter-
nal resistor, R_SET. The external resistor,␣ in combination with
both the reference control amplifier and voltage reference,
REFIO, sets the reference current, I_REF, which is mirrored over
to the segmented current sources with the proper scaling factor.
The full-scale current, I_OUTFS, is exactly thirty-two times the
value of I_REF.
+2.7V TO +3.6V
REFLO
+1.2V REF
AVDD
250pF
ACOM
REFIO
0.1␮F
R_SET
2k⍀
FSADJ
I_REF
SEGMENTED
SWITCHES
CURRENT
SOURCE
ARRAY
IOUTA ^IOUTA V_DIFF = V_OUTA – V_OUTB
LSB
SWITCHES
IOUTB ^IOUTB
R_LOAD
R_LOAD
AD9772
INTERPOLATED
DIGITAL DATA
Figure 31. Block Diagram of Internal DAC, 1.2 V Refer-
ence, and Reference Control Circuits
DAC TRANSFER FUNCTION
The AD9772 provides complementary current outputs, IOUTA
and IOUTB. IOUTA will provide a near full-scale current out-
put, I_OUTFS, when all bits are high (i.e., DAC CODE = 16383)
while IOUTB, the complementary output, provides no current.
REV. 0
–15–