AD9235 Datasheet, PDF (15/32 Pages) Analog Devices – 12-Bit, 20/40/65 MSPS 3 V A/D Converter

AD9235
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 11, the power dissipated by the AD9235 is
proportional to its sample rate. The digital power dissipation
does not vary substantially between the three speed grades
because it is determined primarily by the strength of the digital
drivers and the load on each output bit. The maximum DRVDD
current can be calculated as
I_DRVDD = V_DRVDD × C_LOAD × f_CLK × N
where N is the number of output bits, 12 in the case of the
AD9235. This maximum current occurs when every output bit
switches on every clock cycle, i.e., a full-scale square wave at the
Nyquist frequency, f_CLK/2. In practice, the DRVDD current will
be established by the average number of output bits switching,
which will be determined by the encode rate and the characteris-
tics of the analog input signal.
325
300
AD9235-65
275
250
225
200
175
AD9235-40
150
125
100
AD9235-20
75
50
0.0
10
20
30
40
50
60
SAMPLE RATE (MSPS)
Figure 11. Total Power vs. Sample Rate with f_IN = 10 MHz
For the AD9235-20 speed grade, the digital power consumption
can represent as much as 10% of the total dissipation. Digital
power consumption can be minimized by reducing the capacitive
load presented to the output drivers. The data in Figure 11 was
taken with a 5 pF load on each output driver.
The analog circuitry is optimally biased so that each speed grade
provides excellent performance while affording reduced power
consumption. Each speed grade dissipates a baseline power at
low sample rates that increases linearly with the clock frequency.
By asserting the PDWN pin high, the AD9235 is placed in
standby mode. In this state, the ADC will typically dissipate 1 mW
if the CLK and analog inputs are static. During standby, the
output drivers are placed in a high impedance state. Reassert-
ing the PDWN pin low returns the AD9235 into its normal
operational mode.
Low power dissipation in standby mode is achieved by shutting
down the reference, reference buffer, and biasing networks. The
decoupling capacitors on REFT and REFB are discharged when
entering standby mode, and then must be recharged when returning
to normal operation. As a result, the wake-up time is related to the
time spent in standby mode and shorter standby cycles will result
in proportionally shorter wake-up times. With the recommended
0.1 µF and 10 µF decoupling capacitors on REFT and REFB, it
takes approximately 1 sec to fully discharge the reference buffer
decoupling capacitors and 3 ms to restore full operation.
DIGITAL OUTPUTS
The AD9235 output drivers can be configured to interface with
2.5 V or 3.3 V logic families by matching DRVDD to the digital
supply of the interfaced logic. The output drivers are sized to
provide sufficient output current to drive a wide variety of logic
families. However, large drive currents tend to cause current
glitches on the supplies that may affect converter performance.
Applications requiring the ADC to drive large capacitive loads
or large fan-outs may require external buffers or latches.
As detailed in Table II, the data format can be selected for
either offset binary or twos complement.
Timing
The AD9235 provides latched data outputs with a pipeline delay of
seven clock cycles. Data outputs are available one propagation
delay (t_PD) after the rising edge of the clock signal. Refer to
Figure 1 for a detailed timing diagram.
The length of the output data lines and loads placed on them should
be minimized to reduce transients within the AD9235; these
transients can detract from the converter’s dynamic performance.
The lowest typical conversion rate of the AD9235 is 1 MSPS. At
clock rates below 1 MSPS, dynamic performance may degrade.
VOLTAGE REFERENCE
A stable and accurate 0.5 V voltage reference is built into the
AD9235. The input range can be adjusted by varying the reference
voltage applied to the AD9235, using either the internal reference
or an externally applied reference voltage. The input span of the
ADC tracks reference voltage changes linearly.
If the ADC is being driven differentially through a transformer, the
reference voltage can be used to bias the center tap (common-
mode voltage).
Internal Reference Connection
A comparator within the AD9235 detects the potential at the
SENSE pin and configures the reference into one of four possible
states, which are summarized in Table I. If SENSE is grounded,
Selected
Mode
External Reference
Internal Fixed Reference
Programmable Reference
Internal Fixed Reference
Table I. Reference Configuration Summary
SENSE
Voltage
AVDD
VREF
0.2 V to VREF
AGND to 0.2 V
Internal Switch
Position
N/A
SENSE
SENSE
Internal Divider
Resulting
VREF (V)
N/A
0.5
0.5 × (1 + R2/R1)
1.0
Resulting Differential
Span (V p-p)
2 × External Reference
1.0
2 × VREF (See Figure 13)
2.0
REV. B
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