AD9042_15 Datasheet, PDF (15/24 Pages) Analog Devices – 12-Bit, 41 MSPS Monolithic ADC

When calculating the proper termination resistor, note that the
external load resistor is in parallel with the AD9042 analog
input resistance, 250 Ω. The external resistor value can be
calculated from the following equation:
R_T
=
1
1
−
1
Z 250
where Z is desired impedance.
A dc-coupled input configuration (shown in Figure 35) is
limited by the drive amplifier performance. The on-chip
reference of the AD9042 is buffered using the OP279 dual, rail-
to-rail operational amplifier. The resulting voltage is combined
with the analog source using an AD9631. Pending improvements
in drive amplifiers, this dc-coupled approach is limited to ~75 dB
to 80 dB of dynamic performance depending on which drive
amplifier is used. The AD9631 and OP279 run off ±5 V.
SIGNAL
SOURCE
21Ω
79Ω
AD9631
50Ω
200Ω
0.1µF 114Ω
0pF
TO
50pF
1kΩ
571Ω
49.9Ω
0.1µF
AD9042
AIN
V_OFFSET
V_REF
OP279
(1/2)
OP279
(1/2)
Figure 35. DC-Coupled Analog Input Circuit
POWER SUPPLIES
Care should be taken when selecting a power source. Linear
supplies are strongly recommended because switching supplies
tend to have radiated components that may be received by the
AD9042. Each of the power supply pins should be decoupled as
close to the package as possible using 0.1 μF chip capacitors.
The AD9042 has separate digital and analog 5 V pins. The AVCC
pins are the analog supply pins, and the DVCC pins are the
digital supply pins. Although analog and digital supplies may
be tied together, best performance is achieved when the supplies
are separate. This is because the fast digital output swings can
couple switching noise back into the analog supplies. Note that
AVCC must be held within 5% of 5 V.
AD9042
OUTPUT LOADING
Care must be taken when designing the data receivers for the
AD9042. It is recommended that the digital outputs drive a
series resistor of 499 Ω followed by a CMOS gate such as the
74AC574. To minimize capacitive loading, there should be only
one gate on each output pin. The digital outputs of the AD9042
have a unique constant slew rate output stage. The output slew
rate is about 1 V/ns independent of output loading. A typical
CMOS gate combined with PCB trace and through hole has a
load of approximately 10 pF. Therefore, as each bit switches, 10 mA
of dynamic current per bit flows in or out of the device. A full-
scale transition can cause up to 120 mA (12 bits × 10 mA/bit) of
current to flow through the digital output stage. The series
resistor minimizes the output currents that can flow in the
output stage. These switching currents are confined between
ground and the DVCC pin. Standard TTL gates should be
avoided because they can appreciably add to the dynamic
switching currents of the AD9042.
⎜⎜⎝⎛¹⁰
pF
×
1V
1 ns
⎟⎞
⎟⎠
LAYOUT INFORMATION
The pinout of the AD9042 facilitates ease of use and the
implementation of high frequency/high resolution design
practices. All of the digital outputs are on one side of the
package, and all of the inputs are on the other sides of the
package. It is highly recommended that high quality ceramic
chip capacitors be used to decouple each supply pin to ground
directly at the device. Depending on the configuration used for
the encode and analog inputs, one or more capacitors are
required on those input pins. The capacitors used on the
ENCODE and V_REF pins must be low inductance chip capacitors
as noted previously.
Although a multilayer board is recommended, it is not required
to achieve good results. Care should be taken when placing the
digital output runs. Because the digital outputs have such a high
slew rate, the capacitive loading on the digital outputs should be
minimized. Circuit traces for the digital outputs should be kept
short and connected directly to the receiving gate (broken only
by the insertion of the series resistor). Logic fanout for each bit
should be one CMOS gate.
Rev. B | Page 15 of 24