AD7709ARUZ Datasheet, PDF (15/32 Pages) Analog Devices – 16-Bit-ADC with Switchable Current Sources

AD7709
Status Register (A1, A0 = 0, 0; Power-On-Reset = 00H)
The ADC Status Register is an 8-bit read-only register. To access the ADC Status Register, the user must write to the Communica-
tions Register, selecting the next operation to be a read and load bits A1–A0 with 0, 0. Table VI outlines the bit designations for the
Status Register. SR0 to SR7 indicate the bit location, SR denoting the bits are in the Status Register. SR7 denotes the first bit of the
data stream. The number in brackets indicates the power-on-reset default status of that bit.
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
RDY(0)
0(0)
0(0)
0(0)
ERR(0)
0(0)
STBY(0)
LOCK(0)
Bit
Location
SR7
Bit
Name
RDY
SR6
0
SR5
0
SR4
0
SR3
ERR
SR2
0
SR1
STBY
SR0
LOCK
Table VI. Status Register Bit Designations
Description
Ready Bit for ADC.
Set when data is written to the ADC data register.
The RDY bit is cleared automatically after the ADC data register has been read or a period of time before
the data register is updated with a new conversion result.
This bit is automatically cleared.
This bit is automatically cleared.
This bit is automatically cleared.
ADC Error Bit. This bit is set at the same time as the RDY bit.
Set to indicate that the result written to the ADC data register has been clamped to all zeros or all ones.
Error sources include Overrange, Underrange.
Cleared by a write to the mode bits to initiate a conversion.
This bit is automatically cleared.
Standby Bit Indication.
When this bit is set, the AD7709 is in power-down mode.
This bit is cleared when the ADC is powered up.
PLL Lock Status Bit.
Set if the PLL has locked onto the 32.768 kHz crystal oscillator clock. If the user is worried about exact
sampling frequencies, etc., the LOCK bit should be interrogated and the result discarded if the LOCK
bit is 0.
REV. A
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