AD7451_15 Datasheet, PDF (15/25 Pages) Analog Devices – Pseudo Differential Input, 1 MSPS, 10-/12-Bit ADCs in an 8-Lead SOT-23

AD7441/AD7451
TYPICAL CONNECTION DIAGRAM
Figure 22 shows a typical connection diagram for the device.
In this setup, the GND pin is connected to the analog ground
plane of the system. The VREF pin is connected to the AD780,
a 2.5 V decoupled reference source. The signal source is connected
to the VIN+ analog input via a unity gain buffer. A dc voltage is
connected to the VIN– pin to provide a pseudo ground for the
VIN+ input. The VDD pin is decoupled to AGND with a 10 μF
tantalum capacitor in parallel with a 0.1 μF ceramic capacitor.
The reference pin is decoupled to AGND with a capacitor of at
least 0.1 μF. The conversion result is output in a 16-bit word
with four leading zeros followed by the MSB of the 12-bit or
10-bit result. The 10-bit result of the AD7441 is followed by two
trailing zeros.
V_REF
p-p
DC INPUT
VOLTAGE
0.1µF
10µF
V_DD AD7441/
AD7451
V_IN+
SCLK
2.7V TO 5.25V
SUPPLY
SERIAL
INTERFACE
SDATA
µC/µP
V_IN–
V_REF
CS
GND
0.1µF
2.5V
AD780
Figure 22. Typical Connection Diagram
ANALOG INPUT
The AD7441/AD7451 have a pseudo differential analog input.
The VIN+ input is coupled to the signal source and must have an
amplitude of VREF p-p to make use of the full dynamic range of
the part. A dc input is applied to the VIN–. The voltage applied to
this input provides an offset from ground or a pseudo ground
for the VIN+ input. Pseudo differential inputs separate the analog
input signal ground from the ADC ground, allowing dc common-
mode voltages to be cancelled.
Because the ADC operates from a single supply, it is necessary
to level shift ground-based bipolar signals to comply with the
input requirements. An op amp (for example, the AD8021) can
be configured to rescale and level shift a ground-based (bipolar)
signal so that it is compatible with the input range of the AD7441/
AD7451 (see Figure 23).
When a conversion takes place, the pseudo ground corresponds
to 0, and the maximum analog input corresponds to 4096 for
the AD7451 and 1024 for the AD7441.
+1.25V
0V
–1.25V
R
V_IN+
3R
R
2.5V
R
1.25V
0V
0.1µF
V_IN+
AD7441/
AD7451
V_IN–
V_REF
EXTERNAL
V_REF (2.5V)
Figure 23. Op Amp Configuration to Level Shift a Bipolar Input Signal
ANALOG INPUT STRUCTURE
Figure 24 shows the equivalent circuit of the analog input
structure of the AD7441/AD7451. The four diodes provide
ESD protection for the analog inputs. Care must be taken to
ensure that the analog input signals never exceed the supply
rails by more than 300 mV. This causes these diodes to become
forward-biased and start conducting into the substrate. These
diodes can conduct up to 10 mA without causing irreversible
damage to the part. The C1 capacitors (see Figure 24) are
typically 4 pF and can be attributed primarily to pin capaci-
tance. The resistors are lumped components made up of
the on resistance of the switches. The value of these resistors
is typically about 100 Ω. The C2 capacitors are the ADC
sampling capacitors and have a capacitance of 16 pF typically.
For ac applications, removing high frequency components from
the analog input signal through the use of an RC low-pass filter
on the relevant analog input pins is recommended. In applica-
tions where harmonic distortion and the signal-to-noise ratio
are critical, it is recommended that the analog input be driven
from a low impedance source. Large source impedances
significantly affect the ac performance of the ADC, which can
necessitate the use of an input buffer amplifier. The choice of
the amplifier is a function of the particular application.
V_DD
D
V_IN+
C1
D
R1 ^C2
V_IN–
C1
V_DD
D
D
R1 ^C2
Figure 24. Equivalent Analog Input Circuit;
Conversion Phase—Switches Open;
Track Phase—Switches Closed
Rev. D | Page 14 of 24