AD5624 Datasheet, PDF (15/24 Pages) Analog Devices – 2.7 V to 5.5 V, 450 μA, Rail-to-Rail Output, Quad, 12-/16-Bit nanoDACs

THEORY OF OPERATION
D/A SECTION
The AD5624/AD5664 DACs are fabricated on a CMOS process.
The architecture consists of a string DAC followed by an output
buffer amplifier. Figure 29 shows a block diagram of the DAC
architecture.
DAC
REGISTER
V_DD
REF (+)
RESISTOR
STRING
REF (–)
OUTPUT
AMPLIFIER
(GAIN = +2)
V_OUT
GND
Figure 29. DAC Architecture
Since the input coding to the DAC is straight binary, the ideal
output voltage is given by
V_OUT
= V_REFIN
×
⎜⎝⎛
D
2^N
⎟⎠⎞
where:
D is the decimal equivalent of the binary code that is loaded to
the DAC register:
0 to 4095 for AD5624 (12 bit).
0 to 65535 for AD5664 (16 bit).
N is the DAC resolution.
RESISTOR STRING
The resistor string is shown in Figure 30. It is simply a string of
resistors, each of value R. The code loaded to the DAC register
determines at which node on the string the voltage is tapped off
to be fed into the output amplifier. The voltage is tapped off by
closing one of the switches connecting the string to the
amplifier. Because it is a string of resistors, it is guaranteed
monotonic.
OUTPUT AMPLIFIER
The output buffer amplifier can generate rail-to-rail voltages on
its output, which gives an output range of 0 V to VDD. It can drive
a load of 2 kΩ in parallel with 1000 pF to GND. The source and
sink capabilities of the output amplifier can be seen in Figure 17.
The slew rate is 1.8 V/μs with a ¼ to ¾ full-scale settling time of
7 μs.
AD5624/AD5664
R
R
R
TO OUTPUT
AMPLIFIER
R
R
Figure 30. Resistor String
SERIAL INTERFACE
The AD5624/AD5664 have a 3-wire serial interface (SYNC,
SCLK, and DIN) that is compatible with SPI, QSPI, and
MICROWIRE interface standards as well as with most DSPs.
See Figure 2 for a timing diagram of a typical write sequence.
The write sequence begins by bringing the SYNC line low. Data
from the DIN line is clocked into the 24-bit shift register on the
falling edge of SCLK. The serial clock frequency can be as high
as 50 MHz, making the AD5624/AD5664 compatible with high
speed DSPs. On the 24^th falling clock edge, the last data bit is
clocked in and the programmed function is executed, that is, a
change in DAC register contents and/or a change in the mode
of operation. At this stage, the SYNC line can be kept low or be
brought high. In either case, it must be brought high for a
minimum of 15 ns before the next write sequence so that a
falling edge of SYNC can initiate the next write sequence. Since
the SYNC buffer draws more current when VIN = 2.0 V than it
does when VIN = 0.8 V, SYNC should be idled low between
write sequences for even lower power operation. It must,
however, be brought high again just before the next write
sequence.
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