EVAL-ADE7755ZEB Datasheet, PDF (14/20 Pages) Analog Devices – Energy Metering IC with Pulse Output

ADE7755
Channel 2 (Voltage Channel)
The output of the line voltage transducer is connected to the
ADE7755 at this analog input. Channel 2 is a fully differential
voltage input. The maximum peak differential signal on Channel 2
is ±660 mV. Figure 25 illustrates the maximum signal levels that
can be connected to Channel 2 of the ADE7755.
V2
+660mV
V_CM
DIFFERENTIAL INPUT
±660mV MAX PEAK
COMMON-MODE
±100mV MAX
V2P
V2 _V2N
V_CM
–660mV
AGND
Figure 25. Maximum Signal Levels, Channel 2
Channel 2 must be driven from a common-mode voltage, that
is, the differential voltage signal on the input must be referenced
to a common mode (usually AGND). The analog inputs of the
ADE7755 can be driven with common-mode voltages of up to
100 mV with respect to AGND. However, best results are achieved
using a common mode equal to AGND.
TYPICAL CONNECTION DIAGRAMS
Figure 26 shows a typical connection diagram for Channel 1. A
current transformer (CT) is the current transducer selected for
this example. Note that the common-mode voltage for Channel 1
is AGND and is derived by center-tapping the burden resistor to
AGND. This provides the complementary analog input signals for
V1P and V1N. The CT turns ratio and burden resistor Rb are
selected to give a peak differential voltage of ±470 mV/gain at
maximum load.
CT
Rb
Rf
±470mV
GAIN
V1P
Cf
V1N
IP
AGND
Rf
Cf
PHASE NEUTRAL
Figure 26. Typical Connection for Channel 1
Figure 27 shows two typical connections for Channel 2. The first
option uses a potential transformer (PT) to provide complete
isolation from the power line. In the second option, the ADE7755
is biased around the neutral wire, and a resistor divider provides
a voltage signal that is proportional to the line voltage. Adjusting
the ratio of Ra, Rb, and VR is also a convenient way of carrying
out a gain calibration on the meter.
PT
Rf
PHASE NEUTRAL
±660mV
Rf
AGND
V2P
Cf
V2N
Cf
Ra¹
Cf
Rb¹
±660mV
VR¹
V2P
Rf
V2N
PHASE NEUTRAL
1_{Ra >> Rb + VR}
Cf
Rb + VR = Rf
Figure 27. Typical Connections for Channel 2
POWER SUPPLY MONITOR
The ADE7755 contains an on-chip power supply monitor. The
analog supply (AVDD) is continuously monitored by the ADE7755.
If the supply is less than 4 V ± 5%, the ADE7755 resets. This is
useful to ensure correct device startup at power-up and power-
down. The power supply monitor has built-in hysteresis and
filtering. These features give a high degree of immunity to false
triggering due to noisy supplies.
In Figure 28, the trigger level is nominally set at 4 V. The
tolerance on this trigger level is about ±5%. The power supply
and decoupling for the part should be such that the ripple at
AVDD does not exceed 5 V ± 5%, as specified for normal
operation.
AV_DD
5V
4V
0V
TIME
INTERNAL
RESET ^RESET
ACTIVE
RESET
Figure 28. On-Chip Power Supply Monitor
Rev. A | Page 14 of 20