ADUM7440 Datasheet, PDF (14/20 Pages) Analog Devices – 1 kV RMS Quad-Channel Digital Isolators

ADuM7440/ADuM7441/ADuM7442
APPLICATIONS INFORMATION
PC BOARD LAYOUT
The ADuM744x digital isolators require no external interface
circuitry for the logic interfaces. Power supply bypassing is
strongly recommended at the input and output supply pins
(see Figure 16). A total of four bypass capacitors should be
connected between Pin 1 and Pin 2 for VDD1A, between Pin 7
and Pin 8 for VDD1B, between Pin 9 and Pin 10 for VDD2B, and
between Pin 15 and Pin 16 for VDD2A. Supply VDD1A Pin 1 and
VDD1B Pin 7 should be connected together and supply VDD2B
Pin 10 and VDD2A Pin 16 should be connected together. The
capacitor values should be between 0.01 μF and 0.1 μF. The
total lead length between both ends of the capacitor and the
power supply pin should not exceed 20 mm.
V_DD1A
GND₁
V_IA
V_IB
V_IC/V_OC
V_ID/V_OD
V_DD1B
GND₁
V_DD2A
GND₂
V_OA
V_OB
V_OC/V_IC
V_OD/V_ID
V_DD2B
GND₂
Figure 16. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients, it
is important to minimize board coupling across the isolation
barrier. Furthermore, users should design the board layout
so that any coupling that does occur equally affects all pins
on a given component side. Failure to ensure this can cause
voltage differentials between pins exceeding the absolute
maximum ratings of the device, thereby leading to latch-up
or permanent damage.
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The input-to-
output propagation delay time for a high-to-low transition may
differ from the propagation delay time of a low-to-high
transition.
INPUT (V_Ix)
OUTPUT (V_Ox)
t_PLH
t_PHL
50%
50%
Figure 17. Propagation Delay Parameters
Pulse width distortion is the maximum difference between
these two propagation delay values and an indication of how
accurately the timing of the input signal is preserved.
Channel-to-channel matching refers to the maximum amount
the propagation delay differs between channels within a single
ADuM744x component.
Propagation delay skew refers to the maximum amount the
propagation delay differs between multiple ADuM744x
components operating under the same conditions.
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
Positive and negative logic transitions at the isolator input
cause narrow (~1 ns) pulses to be sent to the decoder using the
transformer. The decoder is bistable and is, therefore, either set
or reset by the pulses, indicating input logic transitions. In the
absence of logic transitions at the input for more than ~1 μs, a
periodic set of refresh pulses indicative of the correct input state
is sent to ensure dc correctness at the output. If the decoder
receives no internal pulses of more than approximately 5 μs,
the input side is assumed to be unpowered or nonfunctional,
in which case the isolator output is forced to a default high state
by the watchdog timer circuit.
The magnetic field immunity of the ADuM744x is determined
by the changing magnetic field, which induces a voltage in the
transformer’s receiving coil large enough to either falsely set or
reset the decoder. The following analysis defines the conditions
under which this can occur. The 3 V operating condition of the
ADuM744x is examined because it represents the most suscep-
tible mode of operation.
The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus
establishing a 0.5 V margin in which induced voltages can be
tolerated. The voltage induced across the receiving coil is given by
V = (−dβ / dt) ∑ π rn²; n = 1, 2, … , N
where:
β is magnetic flux density (gauss).
rn is the radius of the n^th turn in the receiving coil (cm).
N is the number of turns in the receiving coil.
Given the geometry of the receiving coil in the ADuM744x and
an imposed requirement that the induced voltage be, at most,
50% of the 0.5 V margin at the decoder, a maximum allowable
magnetic field at a given frequency can be calculated. The result
is shown in Figure 18.
Rev. 0 | Page 14 of 20