ADUC816 Datasheet, PDF (14/68 Pages) Analog Devices – MicroConverter-R, Dual-Channel 16-Bit ADCs with Embedded Flash MCU

ADuC816
Parameter
Min
Typ
Max
Unit
SPI MASTER MODE TIMING (CPHA = 1)
t_SL
SCLOCK Low Pulsewidth*
t_SH
SCLOCK High Pulsewidth*
t_DAV
Data Output Valid after SCLOCK Edge
t_DSU
Data Input Setup Time before SCLOCK Edge 100
t_DHD
Data Input Hold Time after SCLOCK Edge
100
t_DF
Data Output Fall Time
t_DR
Data Output Rise Time
t_SR
SCLOCK Rise Time
t_SF
SCLOCK Fall Time
630
ns
630
ns
50
ns
ns
ns
10
25
ns
10
25
ns
10
25
ns
10
25
ns
*Characterized under the following conditions:
a. Core clock divider bits CD2, CD1, and CD0 bits in PLLCON SFR set to 0, 1, and 1 respectively, i.e., core clock frequency = 1.57 MHz and
b. SPI bit-rate selection bits SPR1 and SPR0 bits in SPICON SFR set to 0 and 0 respectively.
Figure
8
8
8
8
8
8
8
8
8
SCLOCK
(CPOL = 0)
SCLOCK
(CPOL = 1)
MOSI
MISO
t_SH
t_SL
t_SR
t_SF
t_DAV
t_DF
MSB
t_DR
BITS 6 – 1
LSB
MSB IN
BITS 6 – 1
LSB IN
t_DSU t_DHD
Figure 8. SPI Master Mode Timing (CPHA = 1)
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