ADF4211_15 Datasheet, PDF (14/20 Pages) Analog Devices – Dual RF/IF PLL Frequency Synthesizers

ADF4210/ADF4211/ADF4212/ADF4213
Table V. RF R Latch Map
RF R COUNTER LATCH
RF CP CURRENT
SETTING
15-BIT REFERENCE COUNTER
CONTROL
BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
RF
CP2
RF
CP1
RF
CP0
P12
P11
P10
P9
R15
R14
R13
R12
R11
R10
R9
DB9
R8
DB8
R7
DB7
R6
DB6 DB5 DB4 DB3 DB2 DB1 DB0
R5 R4 R3 R2 R1 C2 (1) C1 (0)
R15
R14
R13
..........
R3
R2
R1
DIVIDE RATIO
0
0
0
..........
0
0
1
1
0
0
0
..........
0
1
0
2
0
0
0
..........
0
1
1
3
0
0
0
..........
1
0
0
4
.
.
.
..........
.
.
.
.
.
.
.
..........
.
.
.
.
.
.
.
..........
.
.
.
.
1
1
1
..........
1
0
0
32764
1
1
1
..........
1
0
1
32765
1
1
1
..........
1
1
0
32766
1
1
1
..........
1
1
1
32767
P9 RF PD POLARITY
0
NEGATIVE
1
POSITIVE
P10 CHARGE PUMP OUTPUT
0
NORMAL
1
THREE-STATE
FROM IF R LATCH
P12
P11
P4
P3
MUXOUT
0
0
0
0
LOGIC LOW STATE
0
0
0
1
IF ANALOG LOCK DETECT
0
0
1
0
IF REFERENCE DIVIDER OUTPUT
0
0
1
1
IF N DIVIDER OUTPUT
0
1
0
0
RF ANALOG LOCK DETECT
0
1
0
1
RF/IF ANALOG LOCK DETECT
0
1
1
0
IF DIGITAL LOCK DETECT
0
1
1
1
LOGIC HIGH STATE
1
0
0
0
RF REFERENCE DIVIDER OUTPUT
1
0
0
1
RF N DIVIDER OUTPUT
1
0
1
0
THREE-STATE OUTPUT
1
0
1
1
IF COUNTER RESET
1
1
0
0
RF DIGITAL LOCK DETECT
1
1
0
1
RF/IF DIGITAL LOCK DETECT
1
1
1
0
RF COUNTER RESET
1
1
1
1
IF AND RF COUNTER RESET
RF CP2
0
0
0
0
1
1
1
1
RF CP1
0
0
1
1
0
0
1
1
RF CP0
0
1
0
1
0
1
0
1
1.5k⍀
1.125
2.25
3.375
4.5
5.625
6.75
7.7875
9.0
I_CP (mA)
2.7k⍀
0.625
1.25
1.875
2.5
3.125
3.75
4.375
5.0
5.6k⍀
0.301
0.602
0.904
1.205
1.506
1.808
2.109
2.411
–14–
REV. A