AD9751_15 Datasheet, PDF (14/28 Pages) Analog Devices – 10-Bit, 300 MSPS

AD9751
Equations 7 and 8 highlight some of the advantages of operating
the AD9751 differentially. First, the differential operation helps
cancel common-mode error sources associated with I_OUTA and
I_OUTB such as noise, distortion, and dc offsets. Second, the
differential code-dependent current and subsequent voltage, V_DIFF,
is twice the value of the single-ended voltage output (i.e., V_OUTA
or V_OUTB), thus providing twice the signal power to the load.
Note that the gain drift temperature performance for a single-
ended (V_OUTA and V_OUTB) or differential output (V_DIFF) of the
AD9751 can be enhanced by selecting temperature tracking
resistors for R_LOAD and R_SET due to their ratiometric relation-
ship, as shown in Equation 8.
ANALOG OUTPUTS
The AD9751 produces two complementary current outputs,
I_OUTA and I_OUTB, that may be configured for single-ended or
differential operation. I_OUTA and I_OUTB can be converted into
complementary single-ended voltage outputs, V_OUTA and V_OUTB,
via a load resistor, R_LOAD, as described by Equations 5 through 8
in the DAC Transfer Function section. The differential voltage,
V_DIFF, existing between V_OUTA and V_OUTB can also be converted
to a single-ended voltage via a transformer or differential ampli-
fier configuration. The ac performance of the AD9751 is optimum
and is specified using a differential transformer-coupled output in
which the voltage swing at I_OUTA and I_OUTB is limited to ± 0.5 V.
If a single-ended unipolar output is desirable, I_OUTA should be
selected as the output, with I_OUTB grounded.
The distortion and noise performance of the AD9751 can be
enhanced when it is configured for differential operation. The
common-mode error sources of both I_OUTA and I_OUTB can be
significantly reduced by the common-mode rejection of a trans-
former or differential amplifier. These common-mode error
sources include even-order distortion products and noise. The
enhancement in distortion performance becomes more signifi-
cant as the frequency content of the reconstructed waveform
increases. This is due to the first order cancellation of various
dynamic common-mode distortion mechanisms, digital feed-
through, and noise.
Performing a differential-to-single-ended conversion via a
transformer also provides the ability to deliver twice the recon-
structed signal power to the load (i.e., assuming no source
termination). Since the output currents of I_OUTA and I_OUTB are
complementary, they become additive when processed differen-
tially. A properly selected transformer will allow the AD9751 to
provide the required power and voltage levels to different loads.
Refer to Applying the AD9751 section for examples of various
output configurations.
The output impedance of I_OUTA and I_OUTB is determined by the
equivalent parallel combination of the PMOS switches associ-
ated with the current sources and is typically 100 kΩ in parallel
with 5 pF. It is also slightly dependent on the output voltage
(i.e., V_OUTA and V_OUTB) due to the nature of a PMOS device.
As a result, maintaining I_OUTA and/or I_OUTB at a virtual ground
via an I-V op amp configuration will result in the optimum dc
linearity. Note that the INL/DNL specifications for the AD9751
are measured with I_OUTA and I_OUTB maintained at virtual ground
via an op amp.
I_OUTA and I_OUTB also have a negative and positive voltage
compliance range that must be adhered to in order to achieve
optimum performance. The negative output compliance range
of –1.0 V is set by the breakdown limits of the CMOS process.
Operation beyond this maximum limit may result in a break-
down of the output stage and affect the reliability of the AD9751.
The positive output compliance range is slightly dependent on
the full-scale output current, I_OUTFS. It degrades slightly from its
nominal 1.25 V for an I_OUTFS = 20 mA to 1.00 V for an I_OUTFS
= 2 mA. The optimum distortion performance for a single-
ended or differential output is achieved when the maximum
full-scale signal at I_OUTA and I_OUTB does not exceed 1.0 V.
Applications requiring the AD9751’s output (i.e., V_OUTA and/or
V_OUTB) to extend its output compliance range should size R_LOAD
accordingly. Operation beyond this compliance range will adversely
affect the AD9751’s linearity performance and subsequently
degrade its distortion performance.
DIGITAL INPUTS
The AD9751’s digital input consists of two channels of 10 data
input pins each and a pair of differential clock input pins. The
10-bit parallel data inputs follow standard straight binary coding
where DB9 is the most significant bit (MSB) and DB0 is the
least significant bit (LSB). I_OUTA produces a full-scale output
current when all data bits are at Logic 1. I_OUTB produces a
complementary output with the full-scale current split between
the two outputs as a function of the input code.
The digital interface is implemented using an edge-triggered
master slave latch. With the PLL active or disabled, the DAC
output is updated twice for every input latch rising edge, as
shown in Figures 7 and 11. The AD9751 is designed to support
an input data rate as high as 150 MSPS, giving a DAC output
update rate of 300 MSPS. The setup-and-hold times can also be
varied within the clock cycle as long as the specified minimum
times are met. Best performance is typically achieved when the
input data transitions on the falling edge of a 50% duty cycle clock.
The digital inputs are CMOS compatible with logic thresholds,
VTHRESHOLD, set to approximately half the digital positive
supply (DVDD) or
VTHRESHOLD
=
DVDD
2
(^±20%)
The internal digital circuitry of the AD9751 is capable of oper-
ating over a digital supply range of 3.0 V to 3.6 V. As a result,
the digital inputs can also accommodate TTL levels when DVDD
is set to accommodate the maximum high level voltage of the
TTL drivers V_OH(max). A DVDD of 3.0 V to 3.6 V typically
ensures proper compatibility with most TTL logic families.
Figure 14 shows the equivalent digital input circuit for the data
and clock inputs.
DVDD
DIGITAL
INPUT
Figure 14. Equivalent Digital Input
The AD9751 features a flexible differential clock input operating
from separate supplies (i.e., CLKVDD, CLKCOM) to achieve
optimum jitter performance. The two clock inputs, CLK+ and
–14–
REV. C