AD7923 Datasheet, PDF (14/20 Pages) Analog Devices – 4-Channel, 200 kSPS, 12-Bit ADC with Sequencer in 16-Lead TSSOP

AD7923
Reference
An external reference source should be used to supply the 2.5 V
reference to the AD7923. Errors in the reference source will
result in gain errors in the AD7923 transfer function and will
add to the specified full-scale errors of the part. A capacitor of at
least 0.1 mF should be placed on the REF_IN pin. Suitable refer-
ence sources for the AD7923 include the AD780, REF 193, and
the AD1582.
If 2.5 V is applied to the REF_IN pin, the analog input range can
be either 0 V to 2.5 V or 0 V to 5 V, depending on the setting of
the RANGE bit in the Control Register.
MODES OF OPERATION
The AD7923 has a number of different modes of operation, which
are designed to provide flexible power management options. These
options can be chosen to optimize the power dissipation/through-
put rate ratio for differing application requirements. The mode of
operation of the AD7923 is controlled by the power management
bits, PM1 and PM0, in the Control Register, as detailed in
Table III. When power supplies are first applied to the AD7923,
care should be taken to ensure that the part is placed in the required
mode of operation. (See the Powering Up the AD7923 section.)
Normal Mode (PM1 = PM0 = 1)
This mode is intended for the fastest throughput rate perfor-
mance as the user does not have to worry about any power-up
times with the AD7923 remaining fully powered at all time.
Figure 11 shows the general diagram of the operation of the
AD7923 in this mode.
The conversion is initiated on the falling edge of CS and the
track-and-hold will enter hold mode as described in the Serial
Interface section. The data presented to the AD7923 on the
DIN line during the first twelve clock cycles of the data transfer
is loaded into the Control Register (provided WRITE bit is set
to 1). The part will remain fully powered up in Normal Mode
at the end of the conversion as long as PM1 and PM0 are set to
1 in the write transfer during that same conversion. To ensure
continued operation in Normal Mode, PM1 and PM0 must
both be loaded with 1 on every data transfer, assuming a write
operation is taking place. If the WRITE bit is set to 0, the power
management bits will be left unchanged and the part will remain
in Normal Mode.
Sixteen serial clock cycles are required to complete the conversion
and access the conversion result. The track-and-hold will go
back into track on the 14th SCLK falling edge. CS may then
idle high until the next conversion or may idle low until some-
time prior to the next conversion (effectively idling CS low).
For specified performance, the throughput rate should not
exceed 200 kSPS, which means there should be no less than 5 ms
between consecutive falling edges of CS when converting. The
actual frequency of the SCLK used will determine the duration
of the conversion within this 5 ms cycle; however, once a con-
version is complete, and CS has returned high, a minimum of
the quiet time, t_QUIET, must elapse before bringing CS low again
to initiate another conversion.
CS
1
SCLK
12
16
DOUT
2 LEADING ZEROS + 2 CHANNEL IDENTIFIER BITS
+ CONVERSION RESULT
DIN
DATA IN TO CONTROL REGISTER
NOTE: CONTROL REGISTER DATA IS LOADED ON FIRST 12 SCLK CYCLES
Figure 11. Normal Mode Operation
Full Shutdown (PM1 = 1, PM0 = 0)
In this mode, all internal circuitry on the AD7923 is powered
down. The part retains information in the Control Register
during full shutdown. The AD7923 remains in full shutdown
until the power management bits in the Control Register, PM1
and PM0, are changed.
If a write to the Control Register occurs while the part is in
Full Shutdown, with the power management bits changed to
PM0 = PM1 = 1, Normal Mode, the part will begin to power
up on the CS rising edge. The track-and-hold that was in hold
while the part was in full shutdown will return to track on the
14th SCLK falling edge. A full 16-SCLK transfer must occur to
ensure that the Control Register contents are updated; however,
the DOUT line will not be driven during this wake-up transfer.
To ensure that the part is fully powered up, t_{POWER UP} (t₁₂) should
have elapsed before the next CS falling edge; otherwise invalid
data will be read if a conversion is initiated before this time.
Figure 12 shows the general diagram for this sequence.
Auto Shutdown (PM1 = 0, PM0 = 1)
In this mode, the AD7923 automatically enters shutdown at the
end of each conversion when the Control Register is updated.
When the part is in shutdown, the track-and-hold is in Hold Mode.
Figure 13 shows the general diagram of the operation of the
AD7923 in this mode. In Shutdown Mode all internal circuitry
on the AD7923 is powered down. The part retains information
in the Control Register during shutdown. The AD7923 remains
in shutdown until the next CS falling edge it receives. On this
CS falling edge, the track-and-hold that was in hold while the
part was in shutdown will return to track. Wake-up time from
Auto Shutdown is 1 ms maximum, and the user should ensure
that 1 ms has elapsed before attempting a valid conversion.
When running the AD7923 with a 20 MHz clock, one dummy
16 SCLK transfer should be sufficient to ensure that the part is
fully powered up. During this dummy transfer, the contents of the
Control Register should remain unchanged, therefore the WRITE
bit should be 0 on the DIN line. Depending on the SCLK
frequency used, this dummy transfer may affect the achievable
throughput rate of the part, with every other data transfer being
a valid conversion result. If, for example, the maximum SCLK
frequency of 20 MHz was used, the Auto Shutdown Mode
could be used at the full throughout rate of 200 kSPS without
affecting the throughput rate at all. Only a portion of the cycle
time is taken up by the conversion time and the dummy transfer
for wake-up. In this mode, the power consumption of the part is
greatly reduced with the part entering Shutdown at the end of
each conversion. When the Control Register is programmed to
move into Auto Shutdown, it does so at the end of the conversion.
The user can move the ADC in and out of the low power state
by controlling the CS signal.
–14–
REV. 0