AD7910_15 Datasheet, PDF (14/24 Pages) Analog Devices – 250 kSPS, 10-/12-Bit ADCs in 6-Lead SC70

AD7910/AD7920
CONVERTER OPERATION
The AD7910/AD7920 are successive approximation analog-to-
digital converters based around a charge redistribution DAC.
Figure 14 and Figure 15 show simplified schematics of the
ADC. Figure 14 shows the ADC during its acquisition phase.
When SW2 is closed and SW1 is in Position A, the comparator
is held in a balanced condition, and the sampling capacitor
acquires the signal on VIN.
CHARGE
REDISTRIBUTION
DAC
SAMPLING
A ^CAPACITOR
V_IN
SW1
B ACQUISITION
PHASE
SW2
CONTROL
LOGIC
AGND
COMPARATOR
V_DD/2
Figure 14. ADC Acquisition Phase
When the ADC starts a conversion (see Figure 15), SW2 opens
and SW1 moves to Position B, causing the comparator to become
unbalanced. The control logic and charge redistribution DAC are
used to add and subtract fixed amounts of charge from the
sampling capacitor to bring the comparator back into a balanced
condition. When the comparator is rebalanced, the conversion is
complete. The control logic generates the ADC output code.
Figure 16 shows the ADC transfer function.
CHARGE
REDISTRIBUTION
DAC
SAMPLING
A ^CAPACITOR
V_IN
SW1
B CONVERSION SW2
PHASE
CONTROL
LOGIC
AGND
COMPARATOR
V_DD/2
Figure 15. ADC Conversion Phase
ADC TRANSFER FUNCTION
The output coding of the AD7910/AD7920 is straight binary.
The designed code transitions occur at the successive integer
LSB values, that is, 1 LSB, 2 LSBs, and so on. The LSB size is
VDD/4096 for the AD7920 and VDD/1024 for the AD7910. The
ideal transfer characteristic for the AD7910/AD7920 is shown
in Figure 16.
111...111
111...110
111...000
011...111
1LSB = V_DD/1024 (AD7910)
1LSB = V_DD/4096 (AD7920)
000...010
000...001
000...000
0V ^1LSB
+V_DD – 1LSB
ANALOG INPUT
Figure 16. Transfer Characteristic
TYPICAL CONNECTION DIAGRAM
Figure 17 shows a typical connection diagram for the AD7910/
AD7920. VREF is taken internally from VDD and, as such, VDD
should be well decoupled. This provides an analog input range of
0 V to VDD. The conversion result is output in a 16-bit word with
four leading zeros followed by the MSB of the 12-bit or 10-bit
result. Two trailing zeros follow the 10-bit result from the
AD7910.
Alternatively, because the supply current required by the
AD7910/AD7920 is so low, a precision reference can be used as
the supply source to the AD7910/AD7920. An REF19x voltage
reference (REF195 for 5 V or REF193 for 3 V) can be used to
supply the required voltage to the ADC (see Figure 17). This
configuration is especially useful if the power supply is quite
noisy or if the system supply voltages are at a value other than
5 V or 3 V (for example, 15 V). The REF19x outputs a steady
voltage to the AD7910/AD7920. If the low dropout REF193 is
used, the current it needs to supply to the AD7910/AD7920 is
typically 1.2 mA. When the ADC is converting at a rate of
250 kSPS, the REF193 needs to supply a maximum of 1.4 mA to
the AD7910/AD7920. The load regulation of the REF193 is
typically 10 ppm/mA (REF193, VS = 5 V), which results in an
error of 14 ppm (42 μV) for the 1.4 mA drawn from it. This
corresponds to a 0.057 LSB error for the AD7920 with VDD =
3 V from the REF193 and a 0.014 LSB error for the AD7910.
For applications where power consumption is of concern, the
power-down mode of the ADC and the sleep mode of the
REF19x reference should be used to improve power
performance. See the Modes of Operation section.
Rev. C | Page 14 of 24