AD5171BRJZ100-R7 Datasheet, PDF (14/24 Pages) Analog Devices – 64-Position OTP Digital Potentiometer

AD5171
Ignoring the effect of the wiper resistance, the transfer function
is simply
V_W
(D)
=
D
63
V_A
(3)
A more accurate calculation, which includes the wiper
resistance effect, yields
V_W (D) =
D
63
R_AB
+
R_W
R_AB + 2R_W
V_A
(4)
Unlike in rheostat mode where the absolute tolerance is high,
potentiometer mode yields an almost ratiometric function of
D/63 with a relatively small error contributed by the RW terms;
thus, the tolerance effect is almost cancelled. Although the thin
film step resistor (RS) and CMOS switches resistance (RW) have
very different temperature coefficients, the ratiometric adjustment
also reduces the overall temperature coefficient effect to 5 ppm/°C,
except at low value codes where RW dominates.
Potentiometer mode includes other operations such as op amp
input, feedback resistor networks, and voltage scaling applications.
Terminal A, Terminal W, and Terminal B can, in fact, be input
or output terminals provided that |VAB|, |VWA|, and |VWB| do not
exceed VDD to GND.
POWER SUPPLY CONSIDERATIONS
To minimize the package pin count, both the OTP and normal
operating voltage supplies share the same VDD terminal of the
AD5171. The AD5171 employs fuse link technology that requires
4.75 V to 5.25 V for blowing the internal fuses to achieve a
given setting, but normal VDD can be anywhere between 2.7 V
and 5.5 V after the fuse programming process. As a result, dual
voltage supplies and isolation are needed if system VDD is lower
than the required VDD_OTP. The fuse programming supply (either
an on-board regulator or rack-mount power supply) must be
rated at 4.75 V to 5.25 V and able to provide a 100 mA current
for 400 ms for successful one-time programming. Once fuse
programming is complete, the VDD_OTP supply must be removed
to allow normal operation at 2.7 V to 5.5 V; the device then
consumes current in the μA range.
5V
R1
APPLY FOR OTP ONLY
10kΩ
2.7V
V_DD
C1
C2
P1
P2 ^{10µF 0.1µF}
AD5171
P1 = P2 = FDV302P, NDS0610
When operating at 2.7 V, use of the bidirectional low threshold
P-Ch MOSFETs is recommended for the isolation of the supply.
As shown in Figure 29, this assumes that the 2.7 V system
voltage is applied first, and the P1 and P2 gates are pulled to
ground, thus turning on P1 and, subsequently, P2. As a result,
VDD of the AD5171 approaches 2.7 V. When the AD5171 setting
is found, the factory tester applies the VDD_OTP to both the VDD
and the MOSFETs gates, thus turning off P1 and P2. The OTP
command should be executed at this time to program the
AD5171 while the 2.7 V source is protected. Once the fuse
programming is complete, the tester withdraws the VDD_OTP and
the setting of the AD5171 is permanently fixed.
The AD5171 achieves the OTP function through blowing
internal fuses. Users should always apply the 4.75 V to
5.25 V one-time program voltage requirement at the first
fuse programming attempt. Failure to comply with this
requirement may lead to a change in the fuse structures,
rendering programming inoperable.
Care should be taken when SCL and SDA are driven from a low
voltage logic controller. Users must ensure that the logic high
level is between 0.7 V × VDD and VDD. Refer to the Level Shifting
for Different Voltage Operation section.
Poor PCB layout introduces parasitics that may affect the fuse
programming. Therefore, it is recommended that a 10 μF
tantalum capacitor be added in parallel with a 1 nF ceramic
capacitor as close as possible to the VDD pin. The type and value
chosen for both capacitors are important. This combination of
capacitor values provides both a fast response and larger supply
current handling with minimum supply droop during transients.
As a result, these capacitors increase the OTP programming
success by not inhibiting the proper energy needed to blow the
internal fuses. Additionally, C1 minimizes transient disturbance
and low frequency ripple, while C2 reduces high frequency
noise during normal operation.
ESD PROTECTION
Digital inputs SDA and SCL are protected with a series input
resistor and parallel Zener ESD structures (see Figure 30).
340Ω
LOGIC
GND
Figure 30. ESD Protection of Digital Pins
Figure 29. 5 V OTP Supply Isolated from the 2.7 V Normal Operating Supply;
the VDD_OTP supply must be removed once OTP is complete.
Rev. D | Page 14 of 24