AD5162_15 Datasheet, PDF (14/20 Pages) Analog Devices – Dual, 256-Position, SPI Digital Potentiometer

AD5162
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
wiper to B and wiper to A, proportional to the input voltage at
A to B. Unlike the polarity of V_DD to GND, which must be
positive, voltage across A to B, W to A, and W to B can be at
either polarity.
V_I
A
W
V_O
B
Figure 35. Potentiometer Mode Configuration
If ignoring the effect of the wiper resistance for approximation,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at the wiper to B, starting at 0 V up
to 1 LSB less than 5 V. Each LSB of voltage is equal to the voltage
applied across the A and B terminals divided by the 256 positions
of the potentiometer divider. The general equation defining the
output voltage at V_W with respect to ground for any valid input
voltage applied to Terminal A and Terminal B is
V_W
(D)
=
D
256
V_A
+
256 − D
256
V_B
(3)
A more accurate calculation, which includes the effect of wiper
resistance, V_W, is
V_W (D)
=
R_WB (D)
R_AB
V_A
+
R_WA (D)
R_AB
V_B
(4)
Operation of the digital potentiometer in the divider mode
results in more accurate operation over temperature. Unlike in
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors R_WA and R_WB, not on the absolute
values. Therefore, the temperature drift reduces to 15 ppm/°C.
ESD PROTECTION
All digital inputs are protected with a series of input resistors
and parallel Zener ESD structures, as shown in Figure 36 and
Figure 37. This applies to the SDI, CLK, and CS digital input pins.
340Ω
LOGIC
GND
Figure 36. ESD Protection of Digital Pins
A, B, W
GND
Figure 37. ESD Protection of Resistor Terminals
TERMINAL VOLTAGE OPERATING RANGE
The AD5162 V_DD and GND power supply defines the boundary
conditions for proper 3-terminal digital potentiometer opera-
tion. Supply signals present on the A, B, and W terminals that
exceed V_DD or GND are clamped by the internal forward-biased
diodes (see Figure 38).
V_DD
A
W
B
GND
Figure 38. Maximum Terminal Voltages Set by V_DD and GND
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance
at the A, B, and W terminals (see Figure 38), it is important to
power V_DD/GND before applying voltage to the A, B, and W
terminals; otherwise, the diode is forward-biased such that V_DD
is powered unintentionally and may affect the rest of the user’s
circuit. The ideal power-up sequence is in the following order:
GND, V_DD, digital inputs, and then V_A, V_B, V_W. The relative
order of powering V_A, V_B, V_W, and the digital inputs is not
important, as long as they are powered after V_DD/GND.
Rev. C | Page 14 of 20