AD1877 Datasheet, PDF (14/18 Pages) Analog Devices – Single-Supply 16-Bit Stereo ADC

AD1877
LRCK
INPUT
BCLK
RDEDGE = LO
INPUT
BCLK
RDEDGE = HI
SOUT
OUTPUT
WCLK
OUTPUT
TAG
OUTPUT
31 32 1
2
3
4
ZEROS
LEFT DATA
MSB
MSB-1 MSB-2
LEFT TAG
MSB LSB
16 17 18
LSB
31 32 1
2
3
4
16 17 18
ZEROS
RIGHT DATA
MSB
MSB-1 MSB-2
LSB
ZEROS
RIGHT TAG
MSB LSB
Figure 9. Serial Data Output Timing: Slave Mode, Left-Justified with No MSB Delay, S/M = Hl,
RLJUST = LO, MSBDLY = Hl
LRCK
INPUT
BCLK
RDEDGE = LO
INPUT
BCLK
RDEDGE = HI
SOUT
OUTPUT
WCLK
OUTPUT
TAG
OUTPUT
32 1 2 3 4 5
ZEROS
LEFT DATA
MSB
MSB-1 MSB-2
LEFT TAG
MSB LSB
17
LSB
31 32 1
2
3
45
17
ZEROS
RIGHT DATA
MSB
MSB-1 MSB-2
LSB
ZEROS
RIGHT TAG
MSB LSB
Figure 10. Serial Data Output Timing: Slave Mode, I²S-Justified, S/M = Hl, RLJUST = LO, MSBDLY = LO
LRCK
OUTPUT
BCLK
RDEDGE = LO
OUTPUT 31 32 1
2
BCLK
RDEDGE = HI
SOUT ^{PREVIOUS DATA}
OUTPUT ^{MSB-14 LSB}
ZEROS
WCLK
OUTPUT
TAG
OUTPUT
LEFT TAG
MSB LSB
15 16 17 18 19
LEFT DATA
MSB
MSB-1 MSB-2
32 1
2
15 16 17 18 19
LSB
ZEROS
RIGHT DATA
MSB
MSB-1 MSB-2
RIGHT TAG
MSB LSB
32 1
2
LSB
ZEROS
LEFT TAG
MSB LSB
Figure 11. Serial Data Output Timing: Master Mode, Right-Justified with No MSB Delay, S/M = LO,
RLJUST = Hl, MSBDLY = Hl
–14–
REV. A