AD1833_15 Datasheet, PDF (14/20 Pages) Analog Devices – Multichannel, 24-Bit, 192 kHz, DAC

AD1833
I²S Timing
I²S timing uses an L/RCLK to define when the data being trans-
mitted is for the left channel and when it is for the right channel.
The L/RCLK is low for the left channel and high for the right
channel. A bit clock running at 64 Ï« f_S is used to clock in the data.
There is a delay of 1 bit clock from the time the L/RCLK signal
changes state to the first bit of data on the SDINx lines. The data
is written MSB first and is valid on the rising edge of the bit clock.
Left-Justified Timing
Left-justified (LJ) timing uses an L/RCLK to define when the
data being transmitted is for the left channel and when it is for
the right channel. The L/RCLK is high for the left channel and
low for the right channel. A bit clock running at 64 ؋ f_S is used
to clock in the data. The first bit of data appears on the SDINx
lines when the L/RCLK toggles. The data is written MSB first
and is valid on the rising edge of the bit clock.
Right-Justified Timing
Right-justified (RJ) timing uses an L/RCLK to define when the
data being transmitted is for the left channel and when it is for
the right channel. The L/RCLK is high for the left channel and
low for the right channel. A bit clock running at 64 Ï« f_S is used
to clock in the data. The first bit of data appears on the SDINx
8-bit clock periods (for 24-bit data) after L/RCLK toggles. In RJ
mode, the LSB of data is always clocked by the last bit clock
before L/RCLK transitions. The data is written MSB first and is
valid on the rising edge of the bit clock.
L/RCLK
INPUT
BCLK
INPUT
SDATA
INPUT
LEFT CHANNEL
MSB
MSB
–1
MSB
–2
LSB
+2
LSB
+1
LSB
RIGHT CHANNEL
MSB
MSB
–1
MSB
–2
LSB
+2
LSB
+1
LSB
MSB
Figure 6. I ²S Timing Diagram
L/RCLK
INPUT
BCLK
INPUT
SDATA
INPUT
MSB
MSB
–1
MSB
–2
LEFT CHANNEL
RIGHT CHANNEL
LSB
+2
LSB
+1
LSB
MSB
MSB
–1
MSB
–2
LSB
+2
LSB
+1
LSB
Figure 7. Left-Justified Timing Diagram
MSB
MSB
–1
L/RCLK
INPUT
BCLK
INPUT
SDATA
INPUT
LSB
LEFT CHANNEL
RIGHT CHANNEL
MSB
MSB
–1
MSB
–2
LSB
+2
LSB
+1
LSB
MSB
MSB
–1
MSB
–2
Figure 8. Right-Justified Timing Diagram
LSB
+2
LSB
+1
LSB
–14–
REV. A