ADE7156_15 Datasheet, PDF (136/152 Pages) Analog Devices – Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Table 150. SPI Interrupt Status SFR (SPISTAT, Address 0xEA)
Bit
Mnemonic Default Description
7
BUSY
0
SPI peripheral busy flag.
BUSY
Result
0
The SPI peripheral is idle.
1
The SPI peripheral is busy transferring data in slave or master mode.
6
MMERR
0
SPI multimaster error flag.
MMERR Result
0
A multiple master error has not occurred.
1
If the SS_EN bit (SPIMOD1, Address 0xE8) is set, enabling the slave select input and
asserting the SS pin while the SPI peripheral is transferring data as a master, this flag is
raised to indicate the error.
Write a 0 to this bit to clear it.
5
SPIRxOF 0
SPI receive overflow error flag. Reading the SPI2CRx SFR clears this bit.
SPIRxOF TIMODE Result
0
X
The SPI2CRx SFR (Address 0x9B) contains valid data.
1
1
This bit is set if the SPI2CRx SFR is not read before the end of the next byte
transfer. If the RxOFW bit (SPIMOD1, Address 0xF8) is set and this condition
occurs, SPI2CRx is overwritten.
4
SPIRxIRQ 0
SPI receive mode interrupt flag. Reading the SPI2CRx SFR clears this bit.
SPIRxIRQ TIMODE Result
0
X
The SPI2CRx register does not contain new data.
1
0
This bit is set when the SPI2CRx register contains new data. If the SPI/I²C
interrupt is enabled, an interrupt is generated when this bit is set. If the SPI2CRx
register is not read before the end of the current byte transfer, the transfer stops
and the SS pin is deasserted.
1
1
The SPI2CRx register contains new data.
3
SPIRxBF
0
Status bit for SPI Rx buffer. When set, the Rx FIFO is full. A read of the SPI2CRx clears this flag.
2
SPITxUF 0
Status bit for SPI Tx buffer. When set, the Tx FIFO is underflowing and data can be written into SPI2CTx
(Address 0x9A). Write a 0 to this bit to clear it.
1
SPITxIRQ 0
SPI transmit mode interrupt flag. Writing new data to the SPI2CTx SFR clears this bit.
SPITxIRQ TIMODE Result
0
X
The SPI2CTx SFR is full.
1
0
The SPI2CTx SFR is empty.
1
1
This bit is set when the SPI2CTx SFR is empty. If the SPI/I²C interrupt is enabled,
an interrupt is generated when this bit is set. If new data is not written into the
SPI2CTx SFR before the end of the current byte transfer, the transfer stops, and
the SS pin is deasserted. Write a 0 to this bit to clear it.
0
SPITxBF
0
Status bit for the SPI Tx buffer. When set, the SPI Tx buffer is full. Write a 0 to this bit to clear it.
SPI PINS
MISO (Master In, Slave Out Data I/O Pin)
The MISO (P0.5/MISO) pin is configured as an input line in
master mode and as an output line in slave mode. The MISO line
on the master (data in) should be connected to the MISO line in
the slave device (data out). The data is transferred as byte-wide
(8-bit) serial data, MSB first.
MOSI (Master Out, Slave In Pin)
The MOSI (P0.4/MOSI/SDATA) pin is configured as an output
line in master mode and as an input line in slave mode. The
MOSI line on the master (data out) should be connected to the
MOSI line in the slave device (data in).The data is transferred as
byte-wide (8-bit) serial data, MSB first.
SCLK (Serial Clock I/O Pin)
The master serial clock (SCLK) is used to synchronize the data
being transmitted and received through the MOSI and MISO
data lines. The SCLK (P0.6/SCLK/T0) pin is configured as an
output in master mode and as an input in slave mode.
In master mode, the bit rate, polarity, and phase of the clock are
controlled by the SPI Configuration SFR 1 (SPIMOD1, Address
0xE8) and SPI Configuration SFR 2 (SPIMOD2, Address 0xE9).
In slave mode, the SPI Configuration SFR 2 (SPIMOD2,
Address 0xE9) must be configured with the phase and polarity
of the expected input clock.
Rev. B | Page 136 of 152