ADE7569_15 Datasheet, PDF (133/152 Pages) Analog Devices – Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
SERIAL PERIPHERAL INTERFACE (SPI)
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 integrate a complete hardware serial peripheral
interface on-chip. The SPI is full duplex so that eight bits of data
are synchronously transmitted and simultaneously received.
This SPI implementation is double buffered, allowing users to
read the last byte of received data while a new byte is shifted in.
The next byte to be transmitted can be loaded while the current
byte is shifted out.
The SPI port can be configured for master or slave operation.
The physical interface to the SPI is via the MISO (P0.5/MISO),
MOSI (P0.4/MOSI/SDATA), SCLK (P0.6/SCLK/T0), and SS
(P0.7/SS/T1) pins, while the firmware interface is via the SPI
Configuration SFR 1 (SPIMOD1, Address 0xE8), the SPI
Configuration SFR 2 (SPIMOD2, Address 0xE9), the SPI
interrupt status SFR (SPISTAT, Address 0xEA), the SPI/I²C
transmit buffer SFR (SPI2CTx, Address 0x9A), and the SPI/I²C
receive buffer SFR (SPI2CRx, Address 0x9B).
Note that the SPI pins are shared with the I²C pins. Therefore, the
user can enable only one interface at a time. The SCPS bit in the
configuration SFR (CFG, Address 0xAF) selects which peripheral
is active.
SPI REGISTERS
Table 145. SPI SFR List
SFR Address
Mnemonic R/W
0x9A
SPI2CTx
W
0x9B
SPI2CRx
R
0xE8
SPIMOD1 R/W
0xE9
SPIMOD2 R/W
0xEA
SPISTAT
R/W
Length (Bits)
8
8
8
8
8
Default
0
0
0x10
0
0
Description
SPI/I²C transmit buffer (see Table 146).
SPI/I²C receive buffer (see Table 147).
SPI Configuration SFR 1 (see Table 148).
SPI Configuration SFR 2 (see Table 149).
SPI/I²C interrupt status (see Table 150).
Table 146. SPI/I²C Transmit Buffer SFR (SPI2CTx, Address 0x9A)
Bit Mnemonic Default
Description
[7:0] SPI2CTx
0
SPI or I²C transmit buffer. When the SPI2CTx SFR is written, its content is transferred to the transmit
FIFO input. When a write is requested, the FIFO output is sent on the SPI or I²C bus.
Table 147. SPI/I²C Receive Buffer SFR (SPI2CRx, Address 0x9B)
Bit Mnemonic Default
Description
[7:0] SPI2CRx
0
SPI or I²C receive buffer. When SPI2CRx SFR is read, one byte from the receive FIFO output is
transferred to SPI2CRx SFR. A new data byte from the SPI or I²C bus is written to the FIFO input.
Rev. B | Page 133 of 152