PKD01 Datasheet, PDF (13/18 Pages) Analog Devices – Monolithic Peak Detector with Reset-and-Hold Mode

PKD01
PEAK HOLD CAPACITOR RECOMMENDATIONS
The hold capacitor (C_H) serves as the peak memory element
and compensating capacitor. Stable operation requires a mini-
mum value of 1000 pF. Larger capacitors may be used to lower
droop rate errors, but acquisition time will increase.
Zero scale error is internally trimmed for C_H = 1000 pF. Other
C_H values will cause a zero scale shift which can be approxi-
mated with the following equation.
( ) ^{1 × 103 pC}
( ) ^∆VZS ^{mV =}
− 0.6 mV
( ) ^CH ^nF
The peak hold capacitor should have very high insulation resis-
tance and low dielectric absorption. For temperatures below
85°C, a polystyrene capacitor is recommended, while a Teflon
capacitor is recommended for high temperature environments.
CAPACITOR GUARDING AND GROUND LAYOUT
Ground planes are recommended to minimize ground path
resistance. Separate analog and digital grounds should be used.
The two ground systems are tied together only at the common
system ground. This avoids digital currents returning to the
system ground through the analog ground path.
14
1
13
2
PKD01 3
12
4
11
10
5
9
6
8
7
C_H
REPEAT ON
“COMPONENT SIDE”
OF PC BOARD IF POSSIBLE
BOTTOM VIEW
Figure 9. C_H Terminal (Pin 4) Guarding. See Text.
The C_H terminal (Pin 4) is a high impedance point. To minimize
gain errors and maintain the PKD01’s inherently low droop rate,
guarding Pin 4 as shown in Figure 9 is recommended.
COMPARATOR
The comparator output high level (V_OH) is set by external resis-
tors. It is possible to optimize noise immunity while interfacing
to all standard logic families—TTL, DTL, and CMOS. Figure
10 shows the comparator output with external level-setting
resistors. Table I gives typical R1 and R2 values for common
circuit conditions.
The maximum comparator high output voltage (V_OH) should be
limited to:
V_OH (maximum) < V+ –2.0 V
With the comparator in the low state (V_OL), the output stage
will be required to sink a current approximately equal to V_C/R1.
COMPARATOR
INPUT
CMP
PKD01
V_C
R1
V_OH
R2
INVERTING DIGITAL V–
COMPARATOR GND
INPUT
( ) R1 = R2
V_{C –1}
V_OH
Figure 10. Comparator Output with External Level-Setting
Resistors
Table I.
V_C V_OH
5 3.5
5 5.0
15 3.5
15 5.0
15 7.5
15 10.0
R1
R2
2.7 kΩ
2.7 kΩ
4.7 kΩ
4.7 kΩ
7.5 kΩ
7.5 kΩ
6.2 kΩ
ϱ
1.5 kΩ
2.4 kΩ
7.5 kΩ
15 kΩ
R1 ≈ ^VC
I_SINK



R2 ≈ _

1^
V_C

− 1^
 V_OH 
PEAK DETECTOR LOGIC CONTROL (RST, DET)
The transconductance amplifier outputs are controlled by the
digital logic signals RST and DET. The PKD01 operational
mode is selected by steering the current (I₁) through Q₁ and Q₂,
thus providing high-speed switching and a predictable logic
threshold. The logic threshold voltage is 1.4 V when digital
ground is at zero volts.
Other threshold voltages (V_TH) may be selected by applying
the formula:
V_TH ≈ 1.4 V + Digital Ground Potential.
For proper operation, digital ground must always be at least
3.5 V below the positive supply and 2.5 V above the negative
supply. The RST or DET signal must always be at least 2.8 V
above the negative supply.
Operating the digital ground at other than zero volts does influence
the comparator output low voltage. The V_OL level is referenced
to digital ground and will follow any changes in digital ground
potential:
V_OL ≈ 0.2 V + Digital Ground Potential.
REV. A
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