DAC8043 Datasheet, PDF (13/16 Pages) Analog Devices – 12-Bit Serial Input Multiplying CMOS D/A Converter

Bipolar Operation (4-Quadrant)
Figure 19 details a suggested circuit for bipolar, or offset binary,
operation. Table 7 shows the digital input to analog output
relationship. The circuit uses offset binary coding. Twos comple-
ment code can be converted to offset binary by software
inversion of the MSB or by the addition of an external inverter
to the MSB input.
Table 7. Bipolar (Offset Binary) Code Table^{1, 2}
Digital Input
Nominal Analog Output
MSB
LSB
(VOUT as Shown in Figure 19)
1111 1111 1111
 V_REF


2047
2048


1000 0000 0001
 V_REF

1
2048

1000 0000 0000
0
0111 1111 1111
 V_REF


1
2048


0000 0000 0001
 V_REF


2047
2048


0000 0000 0000
 V_REF


2048
2048


1 _{Nominal full scale for Figure 19 circuits is given by}
FS

V_REF


2047
2048


2 _{Nominal LSB magnitude for Figure 19 circuits is given by}
LSB

V_REF


1
2048


Resistors R3, R4, and R5 must be selected to match within 0.01%,
and they all must be of the same (preferably metal foil) type to
ensure temperature coefficient matching. Mismatching between
R3 and R4 causes offset and full-scale errors, while an R5 to R4
and R3 mismatch results in full-scale error.
Calibration is performed by loading the DAC register with 1000
0000 0000 and adjusting R1 until VOUT = 0 V. R1 and R2 may be
omitted, adjusting the ratio of R3 to R4 to yield VOUT = 0 V. Full
DAC8043
scale can be adjusted by loading the DAC register with 1111
1111 1111 and either adjusting the amplitude of VREF or the
value of R5 until the desired VOUT is achieved.
Analog/Digital Division
The transfer function for the DAC8043 connected in the
multiplying mode, as shown in Figure 16, Figure 17, and
Figure 19, is
V_O


V_IN


A₁
2¹

A₂
2²

A₃
2³
 ...
A₁₂
2¹²


where AX assumes a value of 1 for an on bit and 0 for an off bit.
The transfer function is modified when the DAC is connected
in the feedback of an operational amplifier, as shown in Figure 18
and becomes



V_O



 V_IN
A_{1 } A_{2 } A₃
2¹ 2² 2³
 ...
A₁₂
2⁴



The previous transfer function is the division of an analog
voltage (VREF) by a digital word. The amplifier goes to the rails
with all bits off because division by zero is infinity. With all bits
on the gain is 1 (±1 LSB). The gain becomes 4096 with the LSB,
Bit 12, on.
DIGITAL
INPUT
LD SRI CLK
V_IN
R_FB
V_DD
5V
DAC8043
I_OUT
V_REF
GND
2
3 ^{OP42 6}
V_OUT
Figure 18. Analog/Digital Divider
R₂
50Ω
R₄
5V
20kΩ
C₁
10.33pF
R₅
20kΩ
V_DD
R_FB
I_OUT
V_IN
V_{REF DAC8043}
R₁
100Ω
CONTROL
GND
BITS
SRI
1/2
OP200
A₁
R₃
10kΩ
1/2
OP200
A₂
CONTROL SERIAL
INPUTS DATA
INPUT
ANALOG
COMMON
Figure 19. Bipolar Operation (4-Quadrant, Offset Binary)
V_OUT
Rev. E | Page 13 of 16