ADUC7036BCPZ Datasheet, PDF (13/132 Pages) Analog Devices – Integrated Precision Battery Sensor for Automotive

ADuC7036
Table 5. SPI Slave Mode Timing (Phase Mode = 0)
Parameter Description
t_SS
SS to SCLK edge
tSL
SCLK low pulse width¹
tSH
SCLK high pulse width¹
tDAV
Data output valid after SCLK edge^{1, 2}
tDSU
Data input setup time before SCLK edge
tDHD
Data input hold time after SCLK edge^{1, 2}
tDF
Data output fall time
tDR
Data output rise time
tSR
SCLK rise time
tSF
SCLK fall time
tDOCS
Data output valid after SS edge²
tSFS
SS high after SCLK edge
Min
Typ
0.5 tSL
(SPIDIV + 1) × tHCLK
(SPIDIV + 1) × tHCLK
0
4 × tUCLK
3.5
3.5
3.5
3.5
0.5 tSL
1 _{tHCLK depends on the clock divider (CD) bits in the POWCON MMR. tHCLK = tUCLK/2}CD_.
2 _{tUCLK = 48.8 ns. It corresponds to the 20.48 MHz internal clock from the PLL before the clock divider.}
Max
(3 × tUCLK) + (2 × tHCLK)
(3 × tUCLK) + (2 × tHCLK)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SS
t_SS
SCLK
(POLARITY = 0)
SCLK
(POLARITY = 1)
t_DOCS
MISO
t_SH
t_SL
t_DAV
t_DF
MSB
t_DR
BITS[6:1]
t_SFS
t_SR
t_SF
LSB
MOSI
MSB IN
BITS[6:1]
LSB IN
t_DSU t_DHD
Figure 5. SPI Slave Mode Timing—Phase Mode = 0
Rev. C | Page 13 of 132