ADSP-2185MBSTZ-266 Datasheet, PDF (13/40 Pages) Analog Devices – DSP Microcomputer

ADSP-2185M
Data Memory
Data Memory (Full Memory Mode) is a 16-bit-wide space used
for the storage of data variables and for memory-mapped control
registers. The ADSP-2185M has 16K words on Data Memory
RAM on-chip. Part of this space is used by 32 memory-mapped
registers. Support also exists for up to two 8K external memory
overlay spaces through the external data bus. All internal accesses
complete in one cycle. Accesses to external memory are timed
using the wait states specified by the DWAIT register and the
wait state mode bit.
Data Memory (Host Mode) allows access to all internal memory.
External overlay access is limited by a single external address
line (A0).
DATA MEMORY
ALWAYS
ACCESSIBLE
AT ADDRESS
0x2000 – 0x3FFF
0x0000 – 0x1FFF
ACCESSIBLE WHEN
DM OVLAY = 0
0x0000 – 0x1FFF¹
EXTERNAL
MEMORY
ACCESSIBLE WHEN
DMOVLAY = 1
ACCESSIBLE WHEN
DMOVLAY = 2
0x0000 – 0x1FFF¹
DATA MEMORY
32 MEMORY
MAPPED
REGISTERS
INTERNAL
8160 WORDS
8K INTERNAL
DMOVLAY = 0
OR
EXTERNAL 8K
DMOVLAY = 1, 2
ADDR
0x3FFF
0x3FE0
0x3FDF
0x2000
0x1FFF
0x0000
NOTE:
1_{SEE TABLE IV FOR DMOVAY BITS}
Figure 5. Data Memory Map
DMOVLAY
0
1
2
Memory
Internal
External Overlay 1
External Overlay 2
Table IV. DMOVLAY Bits
A13
A12:0
Not Applicable
0
1
Not Applicable
13 LSBs of Address Between 0x2000 and 0x3FFF
13 LSBs of Address Between 0x2000 and 0x3FFF
Memory Mapped Registers (New to the ADSP-2185M)
The ADSP-2185M has three memory mapped registers that differ
from other ADSP-21xx Family DSPs. The slight modifications
to these registers (Wait State Control, Programmable Flag and
Composite Select Control, and System Control) provide the
ADSP-2185M’s wait state and BMS control features. Default
bit values at reset are shown; if no value is shown, the bit is unde-
fined at reset. Reserved bits are shown on a grey field. These bits
should always be written with zeros.
SYSTEM CONTROL
15 14 13 12 11 10 9 8 7 6 5 4 3 2
00 00 01 00 000 001
10
11
DM(0x3FFF)
RESERVED
SET TO 0
SPORT0 ENABLE
0 = DISABLE
1 = ENABLE
SPORT1 ENABLE
0 = DISABLE
1 = ENABLE
RESERVED, ALWAYS
SET TO 0
PWAIT
PROGRAM MEMORY
WAIT STATES
DISABLE BMS
0 = ENABLE BMS
1 = DISABLE BMS, EXCEPT WHEN MEMORY
STROBES ARE THREE-STATED
WAITSTATE CONTROL
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DM(0؋3FFE)
DWAIT IOWAIT3 IOWAIT2 IOWAIT1 IOWAIT0
WAIT STATE MODE SELECT
0 = NORMAL MODE (PWAIT, DWAIT, IOWAIT0–3 = N WAIT STATES, RANGING
FROM 0 TO 7)
1 = 2N + 1 MODE (PWAIT, DWAIT, IOWAIT0–3 = 2N + 1 WAIT STATES, RANGING
FROM 0 TO 15)
Figure 6. Wait State Control Register
PROGRAMMABLE FLAG AND COMPOSITE SELECT CONTROL
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 0 1 1 0 0 0 0 0 0 0 0 DM(0x3FE6)
BMWAIT
CMSSEL
0 = DISABLE CMS
1 = ENABLE CMS
PFTYPE
0 = INPUT
1 = OUTPUT
(WHERE BIT: 11-IOM, 10-BM, 9-DM, 8-PM)
Figure 7. Programmable Flag and Composite Control
Register
SPORT1 CONFIGURE
0 = FI, FO, IRQ0, IRQ1, SCLK
1 = SPORT1
NOTE: RESERVED BITS ARE SHOWN ON A GRAY FIELD. THESE BITS SHOULD
ALWAYS BE WRITTEN WITH ZEROS.
Figure 8. System Control Register
I/O Space (Full Memory Mode)
The ADSP-2185M supports an additional external memory
space called I/O space. This space is designed to support simple
connections to peripherals (such as data converters and external
registers) or to bus interface ASIC data registers. I/O space sup-
ports 2048 locations of 16-bit wide data. The lower eleven bits
of the external address bus are used; the upper three bits are
undefined. Two instructions were added to the core ADSP-2100
Family instruction set to read from and write to I/O memory
space. The I/O space also has four dedicated three-bit wait state
registers, IOWAIT0–3, which in combination with the wait state
mode bit, specify up to 15 wait states to be automatically gener-
ated for each of four regions. The wait states act on address
ranges as shown in Table V.
REV. 0
–13–