ADF4218 Datasheet, PDF (13/20 Pages) Analog Devices – Dual RF PLL Frequency Synthesizers

ADF4216/ADF4217/ADF4218
Table III. IF Reference Counter Latch Map
14-BIT REFERENCE COUNTER, R
CONTROL
BITS
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
P4 P3 P2 P5 P1
R14 R13 R12 R11 R10 R9
R8 R7 R6 R5
R4 R3 R2
R1 C2 (0) C1 (0)
R14
R13
R12
..........
R3
R2
R1
DIVIDE RATIO
0
0
0
..........
0
0
1
1
0
0
0
..........
0
1
0
2
0
0
0
..........
0
1
1
3
0
0
0
..........
1
0
0
4
.
.
.
..........
.
.
.
.
.
.
.
..........
.
.
.
.
.
.
.
..........
.
.
.
.
1
1
1
..........
1
0
0
16380
1
1
1
..........
1
0
1
16381
1
1
1
..........
1
1
0
16382
1
1
1
..........
1
1
1
16383
P1 PHASE DETECTOR POLARITY
0
NEGATIVE
1
POSITIVE
P5
I_CP
0
1.25mA
1
4.375mA
P2
CHARGE PUMP
OUTPUT
0
NORMAL
1
THREE-STATE
FROM RFR LATCH
P12
P11
P4
P3
0
0
0
0
0
X
0
X
0
1
0
1
1
X
1
X
1
0
0
0
0
1
1
0
1
1
0
0
0
1
0
0
0
1
1
0
1
0
1
1
1
1
1
1
1
0
1
1
MUXOUT
LOGIC LOW STATE
IF ANALOG LOCK DETECT
IF REFERENCE DIVIDER OUTPUT
IF N DIVIDER OUTPUT
RF ANALOG LOCK DETECT
RF/IF ANALOG LOCK DETECT
RF REFERENCE DIVIDER
RF N DIVIDER
FASTLOCK OUTPUT SWITCH ON
AND CONNECTED TO MUXOUT
IF COUNTER RESET
RF COUNTER RESET
IF AND RF COUNTER RESET
REV. 0
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