AD9912BCPZ Datasheet, PDF (13/40 Pages) Analog Devices – 1 GSPS Direct Digital Synthesizer with 14-Bit DAC

–100
–110
RMS JITTER (100Hz TO 100MHz):
600MHz: 585fs
800MHz: 406fs
–120
–130
–140
800MHz
600MHz
–150
100
1k
10k
100k
1M
10M
100M
FREQUENCY OFFSET (Hz)
Figure 15. Absolute Phase Noise Using HSTL Driver,
SYSCLK = 1 GHz Wenzel Oscillator (SYSCLK PLL Bypassed),
HSTL Output Doubler Enabled
–110
–120
RMS JITTER (100Hz TO 20MHz):
150MHz: 308fs
50MHz: 737fs
–130
–140
–150
150MHz
50MHz
–160
100
10MHz
1k
10k
100k
1M
10M
100M
FREQUENCY OFFSET (Hz)
Figure 16. Absolute Phase Noise Using CMOS Driver at 3.3 V,
SYSCLK = 1 GHz Wenzel Oscillator (SYSCLK PLL Bypassed)
DDS Run at 200 MSPS for 10 MHz Plot
–110
–120
RMS JITTER (100Hz TO 20MHz):
50MHz: 790fs
–130
–140
–150
50MHz
10MHz
–160
100
1k
10k
100k
1M
10M
100M
FREQUENCY OFFSET (Hz)
Figure 17. Absolute Phase Noise Using CMOS Driver at 1.8 V,
SYSCLK = 1 GHz Wenzel Oscillator (SYSCLK PLL Bypassed)
AD9912
800
TOTAL
700
3.3V
1.8V
600
500
400
300
200
100
0
250
375
500
625
750
875
1000
SYSTEM CLOCK FREQUENCY (MHz)
Figure 18. Power Dissipation vs. System Clock Frequency
(SYSCLK PLL Bypassed), fOUT = fSYSCLK/5, HSTL Driver On, CMOS Driver On,
SpurKiller Off
800
700
600
500
400
TOTAL
300
3.3V
1.8V
200
100
0
0
100
200
300
400
OUTPUT FREQUENCY (MHz)
Figure 19. Power Dissipation vs. Output Frequency
SYSCLK = 1 GHz (SYSCLK PLL Bypassed), HSTL Driver On,
CMOS Driver On, SpurKiller Off
10
0
CARRIER:
SFDR W/O SPURKILLER:
399MHz
–63.7dBc
–10
SFDR WITH SPURKILLER: _{–69.3dBc}
FREQUENCY SPAN:
500MHz
RESOLUTION BW:
–20 _{VIDEO BW:}
3kHz
30kHz
–30
–40
–50
THESE TWO SPURS
ELIMINATED WITH
–60
SPURKILLER
–70
–80
–90
–100
0
100
200
300
400
500
FREQUENCY (MHz)
Figure 20. SFDR Comparison With and Without SpurKiller,
SYSCLK = 1 GHz, fOUT = 400 MHz
Rev. F | Page 13 of 40