AD871 Datasheet, PDF (13/16 Pages) Analog Devices – Complete 12-Bit 5 MSPS Monolithic A/D Converter

AD871
The AD871’s CMOS digital output drivers are sized to provide
sufficient output current to drive a wide variety of logic families.
However, large drive currents tend to cause glitches on the sup-
plies and may affect S/(N+D) performance. Applications requir-
ing the AD871 to drive large capacitive loads or large fanout
may require additional decoupling capacitors on DRV_DD and
DV_DD. In extreme cases, external buffers or latches could be
used.
THREE-STATE OUTPUTS
The 44-terminal surface mount AD871 offers three-state out-
puts. The digital outputs can be placed into a three-state mode
by pulling the OUTPUT ENABLE (OEN) pin LOW. Note that
this function is not intended to be used to pull the AD871 on
and off a bus at 5 MHz. Rather, it is intended to allow the ADC
to be pulled off the bus for evaluation or test modes. Also, to
avoid corruption of the sampled analog signal during conversion
(three clock cycles), it is highly recommended that the AD871
be placed on the bus prior to the first sampling.
OEN
As a result, careful selection of the logic family for the clock
driver, as well as the fanout and capacitive load on the clock
line, is important. Jitter-induced errors become more pro-
nounced at higher frequency, large amplitude inputs, where the
input slew rate is greatest.
The AD871 is designed to support a sampling rate of 5 MSPS;
running at slightly faster clock rates may be possible, although at
reduced performance levels. Conversely, some slight perfor-
mance improvements might be realized by clocking the AD871
at slower clock rates. Figure 27 presents the S/(N+D) vs. clock
frequency for a 1 MHz analog input.
75
65
t_DD
t_HL
DATA
OUTPUT
THREE-STATE
ACTIVE
Figure 25. Three-State Output Timing Diagram
For timing budgetary purposes, the typical access and float de-
lay times for the AD871 are 50 ns.
CLOCK INPUT
The AD871 internal timing control uses the two edges of the
clock input to generate a variety of internal timing signals. The
optimal clock input should have a 50% duty cycle; however,
sensitivity to duty cycle is significantly reduced for clock rates of
less than 5 megasamples per second.
+5V
55
3
8
13
FREQUENCY – MHz
Figure 27. Typical S/(N+D) vs. Clock Frequency
f_IN = 1 MHz, Full-Scale Input
The power dissipated by the correction logic and output buffers
is largely proportional to the clock frequency; running at re-
duced clock rates provides a slight reduction in power consump-
tion. Figure 28 illustrates this tradeoff.
1.03
R
D
Q
1.02
75XX74
10MHz
Q
S
CLK
+5V
Figure 26. Divide-by-Two Clock Circuit
Due to the nature of on-chip compensation circuitry, the duty
cycle should be maintained between 40% and 60%, even for
clock rates less than 5 MSPS. One way to realize a 50% duty
cycle clock is to divide down a clock of higher frequency, as
shown in Figure 26.
In this case, a 10 MHz clock is divided by 2 to produce the 5 MHz
clock input for the AD871. In this configuration, the duty cycle
of the 10 MHz clock is irrelevant.
The input circuitry for the CLKIN pin is designed to accommo-
date both TTL and CMOS inputs. The quality of the logic in-
put, particularly the rising edge, is critical in realizing the best
possible jitter performance for the part: the faster the rising
edge, the better the jitter performance.
1.01
0.100
1.100
2.100
3.100
4.100
5.100
FREQUENCY – MHz
Figure 28. Typical Power Dissipation vs. Clock Frequency
ANALOG SUPPLIES AND GROUNDS
The AD871 features separate analog and digital supply and
ground pins, helping to minimize digital corruption of sensitive
analog signals. In general, AV_SS and AV_DD, the analog supplies,
should be decoupled to AGND, the analog common, as close to
the chip as physically possible. Care has been taken to minimize
the signal dependence of the power supply currents; however,
the analog supply currents will be proportional to the reference
input. With REFIN at 2.5 V, the typical current into AV_DD is
REV. A
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